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In this work, four different vacuum sintering temperatures (1250 °C, 1300 °C, 1350 °C and 1400 °C) were studied to determine the optimal process parameters of nano WC–15 wt% (Fe–Ni–Co) and WC–15 wt% Co sintered hard metal alloys. Experimental results showed that the optimal sintering temperatures for nano WC–(Fe–Ni–Co) and WC–Co alloys were 1300 °C and 1350 °C for 1 h, respectively. The sintered nano WC–(Fe–Ni–Co) and WC–Co hard metal alloys showed a good contiguity of 0.44 and 0.42; hardness was enhanced to HRA 90.83 and 90.92; the transverse rupture strength (TRS) increased to 2567.97 and 2860.08 MPa; and KIC was 16.23 and 12.33 MPa√m, respectively. Although the nano WC–(Fe–Ni–Co) alloys possessed a slightly lower TRS value, they exhibited superior fracture toughness (KIC) and hardness similar to that of the nano WC–Co material. Significantly, nano WC–(Fe–Ni–Co) alloys could be sintered at a lower temperature and still retained their excellent mechanical properties.

Cerebral autosomal dominant arteriopathy with subcortical infarcts and leukoencephalopathy (CADASIL) is originally featured with a strong clustering of mutations in NOTCH3 exons 3-6 and leukoencephalopathy with frequent anterior temporal pole involvement. The present study aims at characterizing the genotypic and phenotypic profiles of CADASIL in Taiwan. One hundred and twelve patients with CADASIL from 95 families of Chinese descents in Taiwan were identified by Sanger sequencing of exons 2 to 24 of NOTCH3. Twenty different mutations in NOTCH3 were uncovered, including 3 novel ones, and R544C in exon 11 was the most common mutation, accounting for 70.5% of the pedigrees. Haplotype analyses were conducted in 14 families harboring NOTCH3 R544C mutation and demonstrated a common haplotype linked to NOTCH3 R544C at loci D19S929 and D19S411. Comparing with CADASIL in most Caucasian populations, CADASIL in Taiwan has several distinct features, including less frequent anterior temporal involvement, older age at symptom onset, higher incidence of intracerebral hemorrhage, and rarer occurrence of migraine. Subgroup analyses revealed that the R544C mutation is associated with lower frequency of anterior temporal involvement, later age at onset and higher frequency of cognitive dysfunction. In conclusion, the present study broadens the spectrum of NOTCH3 mutations and provides additional insights for the clinical and molecular characteristics of CADASIL patients of Han-Chinese descents.

The present study aims to discover single nucleotide polymorphisms (SNPs) at the apelin gene (APLN) in relation to arterial stiffness, and to explore its molecular mechanisms. A two-step genetic association study was conducted using 799 and 937 subjects in the screening and validation data, respectively. Four tagging SNPs of APLN were tested. SNP rs3115757 was significantly associated with stiffness parameters (β, Ep and PWV) in women, but not in men. The function of rs3115757 was tagged by rs3115758 which is located in miR-765 binding site in the 3′ untranslated region of APLN. The reporter assay confirmed that different alleles of rs3115758 interfered with miR-765 binding and then modified APLN expression. Over-expression of miR-765 in endothelial cells decreased mRNA and protein levels of APLN, which further inhibited the phosphorylation of eNOS and ERK/Akt/AMPK signaling. Collectively, our data showed that rs3115758 accounts for the susceptibility of arterial stiffening through miR-765-induced APLN repression.

A high-dynamic-range variable optical attenuator (VOA) using a movable shutter, which moves in a tilted-angle direction to the collimate fiber pair, is proposed. The VOA operates in the C+L band with the advantages low cost, high dynamic range of more than 50 dB, low insertion loss of 0.8 dB, low wavelength-dependent loss (WDL), and low polarization-dependent loss of ±0.4 dB and 0.4 dB, respectively, with attenuation of 50 dB. A compact size of 5.0 × 1.5 × 1.5 cm is obtained. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 1000–1002, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21547

Background Cerebrovascular disease is the second leading cause of central nervous system pathology in cancer patients. Cancer-associated hypercoagulation plays an important role in cancer-related stroke. The present study aims to test whether plasma d -dimer levels could predict comorbid malignancy in patients with ischemic stroke. Methods Five hundred sixteen stroke patients with measured d -dimer levels and who were consecutively admitted to our stroke center from 2009 to 2012 were included. Cancer status was determined by medical chart, and 59 patients were identified to have active cancer. An additional 48 cancer patients with stroke were identified from the hospital database. Several d -dimer cutoff levels were used to predict cancer-related stroke. Results Stroke patients with active cancer had significantly higher d -dimer levels than those without cancer (P d -dimer level in stroke patients without cancer was .66 ± 1.83 mg/L, whereas the levels for active cancer patients from the stroke center and hospital database were 5.70 ± 9.63 mg/L and 10.47 ± 12.31 mg/L, respectively. When using d -dimer of .55 mg/L or more and multiple territory infarctions as criteria, the specificity and positive predictive value (PPV) for cancer-related stroke were 99.7% and 92.9%, respectively. When using d -dimer of 5.5 mg/L or more as the cutoff value, the test had a high specificity and PPV regardless the brain magnetic resonance imaging (MRI) findings. Six stroke patients fitting our criteria were confirmed to have occult malignancy after comprehensive cancer survey. Conclusions Extraordinary high d -dimer levels or combining d -dimer and MRI findings may be used as a screening tool to detect malignancy in stroke patients.

Objectives The present study aimed to explore the role of microribonucleic acid (miRNA) Let-7g in regulating endothelial functions. Background Derangement of miRNAs is implicated in the pathogenesis of cardiovascular diseases. Because the transforming growth factor (TGF)-β pathway plays a regulatory role in endothelial functions, miRNAs targeted at TGF-β signal cascade might affect vascular health. Methods Bioinformatics software predicted that Let-7g can influence the TGF-β pathway by targeting 3 genes. The Let-7g's effects on multiple endothelial functions were first tested in endothelial cells (ECs) and then in apolipoprotein E knockout mice. Blood samples from lacunar stroke patients were also examined to further support Let-7g's effects on human subjects. Results Let-7g was experimentally confirmed to knock down the THBS1 , TGFBR1 , and SMAD2 genes in the TGF-β pathway. PAI-I, one of the downstream effectors of the TGF-β pathway, was also down-regulated by Let-7g. Let-7g decreased EC inflammation and monocyte adhesion and increased angiogenesis via the TGF-β pathway. Furthermore, Let-7g reduced EC senescence through increasing SIRT-1 protein. Venous injection of Let-7g inhibitor into apolipoprotein E knockout mice caused overgrowth of vascular intima-media, overexpression of PAI-1, increased macrophage infiltration, and up-regulation of TGF-β downstream genes in the carotid arteries. Let-7g's beneficial effects on EC were reduced, whereas the TGF-β pathway was suppressed by ribonucleic acid interference. Restoration of the TGF-β pathway also attenuated the effects of Let-7g overexpression. Low serum levels of Let-7g were associated with increased circulating PAI-1 levels. Conclusions Decreased Let-7g levels impair endothelial function and increase the risks of cardiovascular diseases through targeting TGF-β and SIRT-1 signaling.

In this work, a multi-layer hierarchical distributed power delivery architecture for TSV 3DIC is proposed. By decoupling global and local power networks, the proposed power delivery architecture can be flexibly configured for different power requests. The decoupled power architectures can also greatly reduce the required decoupling capacitor sizes for voltage stabilization. Meanwhile, a multi-threshold CMOS switched capacitor DC-DC converter with up to 78% power efficiency is implemented in 65nm CMOS for hierarchical distributed power delivery architecture. An adaptive power management technique is presented to work in the local power network to increase the power efficiency. The proposed multi-layer hierarchical distributed power delivery architecture is also very useful for the heterogeneous integration in 3DIC chips.

In this paper, the FNN-BPAI controller is proposed for the nonlinear systems. Firstly, the FNN identifier is utilized to estimate the dynamics of the nonlinear system. These parameters which include weights, means, and standard deviations of the FNN identifier are adjusted by the BP algorithm. Secondly, the initial values which include weights, means, and standard deviations of the FNN identifier and the parameters of the BP algorithm are estimated by the AI estimator. Thirdly, the training process of the AI estimator has four stages which include initialization, crossover, mutation, and evolution. Further, the computation controller is given to calculate the control effect and the hitting controller is utilized to eliminate the uncertainties.

The voltage-/temperature-induced delay estimation error of conventional logical effort is much more severe in near/sub-threshold region. In this paper, super-/near-/sub-threshold logical effort models are proposed to eliminate delay estimation error caused by voltage and temperature variations. These models establish over the four different nanoscale CMOS generations. They also take environmental parameter variations with wide supply voltage 0.1∼1V and full temperature −50∼125oC range into account. The simulation results are using UMC 90-nm, PTM 65-, 45- and 32-nm bulk CMOS technologies, respectively. The average absolute error among the three regions are only 6.01%, 4.12%, 8.01% and 6.55% for UMC 90-nm, PTM 65-, 45- and 32-nm technology, respectively. Proposed models extend the original high performance circuits design in super-threshold region to low power circuit design in near-threshold and sub-threshold regions. They are useful for future green electronics applications.

In this paper, a radial basis function network (RBFN) based automatic generation fuzzy neural network (AGFNN) controller is proposed to control the rotor position of the permanent magnet linear synchronous motor (PMLSM) to track the period reference trajectories. The proposed scheme has not only the advantages of the back-propagation algorithm, in which the parameters of the connected weights are adjusted, but also has advantages of the switching law, momentum term, and RBFN, in which the tracking error and steady state responses will be improved. The structure learning is based on the Mahalanobis distance and the parameter learning is based on the back-propagation algorithm. The simulation results of the proposed controller with the periodic reference trajectories show that the tracking error and steady state responses have the satisfactory performance and own the robustness performance under the parameter variation and external load disturbance.

In this paper, a self-constructing recurrent fuzzy neural network (SCRFNN) method is proposed to control the speed of a permanent-magnet synchronous motor to track periodic reference trajectories. The proposed SCRFNN combines the merits of self-constructing fuzzy neural network (SCFNN) and the recurrent neural network (RNN). The structure learning is based on the partition of input space, and the parameter learning is based on the supervised gradient-decent method. In addition, the Mahalanobis distance (M-distance) formula is employed that the neural network has the ability of identification of the neurons will be generated or not. Finally, the simulated results show that the control effort is robust.

In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130 nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.

In this paper, we deploy power gating technique on a low-power Pseudo SRAM circuit with 3T1D gain cell. A 256-word x 32-BL-pair 3T1D gain cell array is implemented in standard logic technology with TSMC 0.13 um model for multi-bank Pseudo SRAM. Each Pseudo SRAM has its independent access control unit, enabling parallel refresh and read-write accesses to different bank. By employing power gating technique in sense amplifier of 3T1D gain cell array, 15% standby leakage current during sleep mode could be reduced. Also, 12% sensing speed could be enhanced when Pseudo SRAM is operated in normal mode (simulated with TSMC 100 nm technology model).

In this paper, a new single-ended 6-T SRAM cell is proposed. It has a very strong static noise margin (SNM) during read cycles. Meanwhile, data can be easily written because of floating virtual ground and 1-T equalizer insertion within cell. Low-swing writing ability is achieved by these two approaches. A single-ended current-mode sensing amplifier is also presented. This amplifier can sense a very small swing of bitline, equipping with a high noise-rejection and high PVT-tolerance ability. A low-swing 3-port 64times32-bit SRAM macro is simulated in TSMC 130 nm CMOS technology. It consumes a minimum of 725 muW and 658 muW per-port at 1 GHz with 1.2 V supply voltage for read and write power, respectively.

We proposed N-channel power compensated and reconfigurable optical add/drop multiplexer (ROADM) based on the utilization of fiber Bragg gratings (FBGs). Both tunable and fixed fiber Bragg gratings are used in this ROADM. By using the dual-pass amplification scheme, an 8.0 dB optical net gain is achieved with gain variation under ±0.5 dB for each add/drop/pass-through channel. System demonstration bit error rate performance with only 1.2 dB of power penalty in a 10 Gb/sx 4 Ch, 100-km lightwave transmission.

An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of an Analog-to-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.