Search

Objective: The applications of artificial intelligence (AI) are increasing in restorative dentistry; however, the AI performance is unclear for dental professionals. The purpose of this narrative review was to evaluate the applications, functions, and accuracy of AI in diverse aspects of restorative dentistry including caries detection, tooth preparation margin detection, tooth restoration design, metal structure casting, dental restoration/implant detection, removable partial denture design, and tooth shade determination. Overview: An electronic search was performed on Medline/PubMed, Embase, Web of Science, Cochrane, Scopus, and Google Scholar databases. English‐language articles, published from January 1, 2000, to March 1, 2022, relevant to the aforementioned aspects were selected using the key terms of artificial intelligence, machine learning, deep learning, artificial neural networks, convolutional neural networks, clustering, soft computing, automated planning, computational learning, computer vision, and automated reasoning as inclusion criteria. A manual search was also performed. Therefore, 157 articles were included, reviewed, and discussed. Conclusions: Based on the current literature, the AI models have shown promising performance in the mentioned aspects when being compared with traditional approaches in terms of accuracy; however, as these models are still in development, more studies are required to validate their accuracy and apply them to routine clinical practice. Clinical Significance: AI with its specific functions has shown successful applications with acceptable accuracy in diverse aspects of restorative dentistry. The understanding of these functions may lead to novel applications with optimal accuracy for AI in restorative dentistry. [ABSTRACT FROM AUTHOR]

ABSTRACT A two-stage mm-wave variable-gain amplifier is designed and implemented in a 65-nm CMOS technology. A fully symmetric layout has been utilized to suppress the odd-mode of propagation and increase the quality factor in co-planar waveguide transmission lines. Moreover, a new design technique is proposed for implementing decoupling capacitors for mm-wave frequencies. Body-biasing technique is utilized to change the amplifier gain without significant change in the overall power consumption of the circuit. The measurement results show that the amplifier achieves a peak gain of 10 dB with a gain variation range of 25 dB while consuming 12 mW from a 1.2-V supply. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:470-477, 2014. [ABSTRACT FROM AUTHOR]

A design technique to increase the output amplitude and hence the output power of push-push LC-based voltage-controlled oscillators (LC VCOs) is presented that relies on LC resonance boosting of the second harmonic. Measurement results are in good agreement with the results predicted from the analysis. Using the proposed technique, a low-power push-push LC VCO is designed and implemented in 90-nm CMOS. Based on the measurement results, the VCO has a frequency tuning range of 23%, from 20.1 to 24.8 GHz. It exhibits up to 8 dB improvement in its output power at the middle of the frequency band compared to a traditional push-push VCO. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1581-1584, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27599 [ABSTRACT FROM AUTHOR]

Presents a method for the design of the finite-impulse-response prototype filter for maximally decimated overlapped complex-modulated transmultiplexers with near perfect reconstruction property. Values of overlap factor; Frequency selectivity; Data communications application employing multicarrier modulation.

Evaluates several classical and modern receiver architectures used in wideband wireless communication systems. Configurations suitable for integration on a single silicon chip; Advantages and drawbacks of the receiver architectures; Image band problem related to frequency downconversion in radio frequency receivers.

Focuses on the M-channel maximally decimated filter banks and the controlling of distortions in these banks. Design procedure which controls distortion; Review of distortions present in the filter bank.

Soft sensors that can discriminate shear and normal force could help provide machines the fine control desirable for safe and effective physical interactions with people. A capacitive sensor is made for this purpose, composed of patterned elastomer and containing both fixed and sliding pillars that allow the sensor to deform and buckle, much like skin itself. The sensor differentiates between simultaneously applied normal force and shear using summation and differences of signals from four deformable capacitors. Cross talk from shear to normal force is less than 2.5%, and between shear axes is less than 10%. Normal and shear stress sensitivity is 0.49 kPa and 0.31 kPa respectively, with a minimum displacement resolution of 40 μm. In addition, finger proximity is detectable at a range of up to 15 mm. The operation is demonstrated on a simple gripper holding a cup. The combination of features and the straightforward fabrication method make this sensor a candidate for implementation as a sensing skin for humanoid robotics applications. [ABSTRACT FROM AUTHOR]

This paper presents an architecture for differential Colpitts voltage-controlled oscillators (VCOs) in complementary metal–oxide–semiconductor (CMOS) that utilizes three design techniques to extend the tuning range (TR) of the VCO, while maintaining a low phase noise (PN) and a low power consumption. First, a switched-capacitor bank based on a variable capacitive feedback technique is introduced to achieve a wide TR with a minimal PN degradation. Second, a $G_{m}$ -boosting technique using interstage inductors is employed to lower the power consumption and relax VCO startup issues. Third, a dynamic forward-body self-biased technique is used to further reduce the power consumption and PN of the proposed structure. As a proof of concept, a 26.3-GHz differential Colpitts VCO is designed and fabricated in a 65-nm CMOS process. Based on the measurement results, the VCO achieves a PN of −122.1 dBc/Hz at 10-MHz offset from the center frequency, and a TR of 20%. The circuit consumes 2.3 mW from a 1-V supply and excluding the pads occupies a 0.22 mm2 of silicon area. Compared to the recently published CMOS VCOs within the same frequency range, the proposed VCO simultaneously achieves a wide TR, low power dissipation, and low PN, resulting in a figure of merit (FOM) and FOM incorporating the TR (FOM $_{T}$) of −187 and −193 dBc/Hz at 10-MHz offset from the center frequency, respectively. [ABSTRACT FROM AUTHOR]

Vehicular power line communication (VPLC) is being considered as a potential solution to mitigate the increase of complexity and cost of the automotive wiring harness caused by the growth of the number of electronic devices and sensors deployed inside vehicles. This is because VPLC reuses power cables for data communication and, thus, avoids the need for additional communication wires. However, this reuse does not come without problems. One of the challenges for VPLC is the time, frequency, and location dependence of the access impedance, which can cause severe impedance mismatch for the communication signal. Impedance mismatch degrades the signal-to-noise-power ratio at the communication receiver and thus affects transmission reliability. Due to the variable nature of the access impedance, a fixed matching circuit will be inefficient. Hence, in this work, we present an adaptive impedance-matching system, which improves the communication-signal transfer from the transmitting to the receiving device. The system is evaluated via simulations for a wide range of access-impedance test points and $S$- parameters of VPLC networks obtained in previous measurement campaigns. Our simulation results demonstrate that the presented adaptive matching system is able to achieve VPLC signal-power transfer within 30% of the theoretical optimum. This translates to a power gain, up to a factor of 10, which is larger than that of other solutions reported in the literature. [ABSTRACT FROM PUBLISHER]

The frequency-translating hybrid analog-to-digital converter (FTH-ADC) architecture is based on frequency interleaving and decomposing the wideband analog input signal into narrower-bandwidth analog baseband subbands, digitizing them, and performing further signal processing in the digital domain. In this paper, digital compensation techniques to enhance the performance of the FTH-ADC system in the presence of errors due to a variety of mismatches are presented. The effectiveness of these techniques to enhance the performance of the system is confirmed using a proof-of-concept two-channel prototype. [ABSTRACT FROM AUTHOR]

An ultralow-power direct-conversion Bluetooth-low-energy (BLE) receiver (RX) front-end that employs current-reuse and subthreshold techniques is presented. A stacked and self-biased low-noise amplifier (LNA) with active balun consumes 400 μW and achieves a noise figure (NF) of 3.2-dB and a high gain (programmable from 18 to 31 dB), meeting the system specifications over the process, supply voltage, and temperature (PVT) variations. The RX front-end has a measured integrated NF of 5.2 dB from 50 KHz to 1 MHz that corresponds to a sensitivity of −95.1 dBm. At an RX gain of 47 dB, IIP3 was measured at −19.7 dBm. The LC VCO operates at twice the carrier frequency with a tuning range of 4.55 to 5.15 GHz in an integer-N phase-locked loop (PLL). An ultralow-power CML divider is used to generate the LO I/Q. The integrated phase noise (IPN) of the LO at 2.4 GHz is 0.83° with spot phase noise of −119.9 dBc/Hz at 3 MHz frequency offset. The PLL is entirely placed inside the VCO inductor resulting in an overall die area reduction of 8%. A 6-μW automatic dc offset-calibrator avoids saturation of consecutive baseband blocks. Multiple μW-level feedback control loops are used in the design to make it robust over PVT variations. The RX front-end prototype is implemented in a 40-nm LP CMOS process and occupies a silicon area of 0.7 mm2. [ABSTRACT FROM AUTHOR]

This article presents an event-driven ultralow-power radio intended for miniaturized biomedical implants. In its powerlink, the system employs an RF-to-dc converter to scavenge energy from the electromagnetic waves in the 2.4-GHz unlicensed industrial, scientific, and medical (ISM) band. The bidirectional time-division datalink is realized by exploiting the 915-MHz ISM band, and its operation is coordinated by a smart control module, where the cyclic redundancy check is conducted to switch the system between monitoring and interrogation modes. A proof-of-concept radio is fabricated in a 0.13- $\mu \text{m}$ CMOS process with the chip area of 1.4 mm2. Without employing any external components, the radio is robust to process, supply voltage, and body temperature variations, leading to a low-cost and highly integrated wireless solution. During the monitoring mode, the downlink data reception and demodulation are realized by a receiver that consumes $27.5~\mu \text{W}$ while achieving a sensitivity of −69 and −59 dBm at the data rates of 1 and 100 kb/s, respectively. Dissipating peak power of $49.5~\mu \text{W}$ in the interrogation mode, the data transmitter delivers an output power of −30.6 dBm with a data rate of 2.5 Mb/s. [ABSTRACT FROM AUTHOR]

In this article, we present a circuit technique to design a wide tuning range (TR) voltage-controlled oscillator (VCO). The employed technique extends the TR with a minimal adverse effect on the phase noise (PN). In this context, a switchable triple-coupled transformer, implemented utilizing the topmost three metal layers of the process, is proposed to achieve a wide TR and a low PN. In the proposed configuration, the mutual coupling between the loads is increased while canceling the negative effects of the switches on the transformer performance. Depending on the possible states of the switches used in the secondary and tertiary coils, four overlapping frequency sub-bands are introduced. An extensive set of analysis is provided to support the idea. As a proof-of-concept, a 55-GHz VCO is implemented in a 65-nm CMOS process. Based on the measurement results, the VCO achieves an average PN of −111.9 dBc/Hz at 10-MHz offset over the entire frequency range and a TR of ~18%, from 50.1 to 59.8 GHz, exhibiting a figure of merit incorporating the TR (FOM $_{T}$) of −184 dBc/Hz at 10 MHz. The VCO core consumes 6.2 mW from a 1-V supply and, excluding the pads, occupies a compact silicon area of 0.06 mm2. [ABSTRACT FROM AUTHOR]

In this paper, we present a low-power event-driven receiver intended for miniaturized biomedical implants. The fully integrated system can operate by power harvesting from electromagnetic fields using a radio frequency-to-dc converter or through a 0.5-V voltage supply such as a rechargeable battery. Without any external component and calibration overhead, the proposed double-mixing receiver is operating at a frequency of 915-MHz industrial, scientific, and medical band and is robust to process, supply voltage, and body temperature variations. The proof-of-concept receiver is designed and implemented in a 0.13- $\mu \text{m}$ CMOS technology. The system occupies a silicon area of 0.75 mm2 and consumes only 9.1- $\mu \text{W}$ power while achieving a sensitivity of −48 and −39 dBm at the data rate of 1 and 100 kb/s, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a high-efficiency frequency-reconfigurable CMOS power amplifier (PA) design technique is presented at 24 and 28 GHz using integrated tunable neutralization and matching networks. To cope with the adverse effects of gate–drain capacitance ( C\mathrm {gd} ) in millimeter-wave (mm-wave) CMOS PAs in deep-submicrometer technologies, we propose a reconfigurable coupling-coefficient-based transformer. This technique provides optimum neutralization of C\mathrm {gd} in a common-source configuration, while enabling tunable neutralization in a frequency reconfigurable PA. Furthermore, to reconfigure the PA’s input and output matching networks, a low-loss frequency-reconfigurable matching topology using a switched substrate-shield inductor is proposed. The adopted matching network addresses the high loss in a conventional frequency reconfigurable matching approach, while facilitating high efficiency in the proposed PA design. Using the proposed techniques, a class-AB PA is fabricated in a 65-nm CMOS technology. This prototype achieves measured saturated power-added efficiency (PAEsat) of 42.6%, saturated output power ( Po,\mathrm {sat} ) of 14.7 dBm at 24 GHz, and 40.1% PAEsat, and 14.4 dBm Po,\mathrm {sat} at 28 GHz while occupying an active area of only 0.11 mm2. At 24 and 28 GHz, the PA is tested under 16 and 64-quadrature amplitude modulation (QAM) signals with 250 MHz of channel BW. The PA achieves modulated PAE of 15.2%/14.1%, error vector magnitude of −26.4/−26.6 dB, and adjacent channel leakage ratio of −30/−32 dBc at an average output power of 7.1/7 dBm for a 64-QAM signal with 250-MHz BW at 24 and 28 GHz, respectively. To the best of the author’s knowledge, the design presents one of the highest PAEs among mm-wave CMOS PAs reported to date, while it also supports multiband operation. [ABSTRACT FROM PUBLISHER]

A switched substrate-shield inductor (SSI) topology in bulk CMOS is proposed which minimizes parasitic capacitance and substrate losses, while tuned magnetically induced currents facilitate inductor tunability. The high frequency behavior of the induced current is analyzed, resulting in intuitive insights and design guidelines for a high-performance SSI. An SSI prototype in 65-nm bulk CMOS achieves 34% inductance tunability with a quality factor of >10.3. A voltage-controlled oscillator (VCO) using SSI achieves 40.3% tuning range, from 21 to 31.6 GHz, and a phase noise of −119.1 ± 3.7 dBc/Hz at 10-MHz offset frequencies. The VCO core consumes 4.3 ± 0.2 mW from a 1-V supply. [ABSTRACT FROM PUBLISHER]

Fully integrated buck converters are typically operated with a second-order LC low-pass filter and a switching frequency beyond 100 MHz. The motivation for such design choices is to reduce the size of passive components in the LC low-pass filter required for small output voltage ripple. However, in a buck converter with on-chip planar spiral inductors, a fourth-order filter can deliver better performance characteristics without area penalty. This paper presents a comparative study of a fourth-order LC low-pass filter versus a second-order LC low-pass filter with on-chip planar spiral inductors and on-chip capacitors. A fully integrated buck converter is then designed with a quasi-V2 controller to demonstrate the benefits of a fourth-order LC low-pass filter. The prototype chip, which is implemented in a 65-nm CMOS process, produces a nominal voltage of 0.7 V from a 1-V supply. The fourth-order LC low-pass filter uses a total inductance of 1.8 nH and a total capacitance of 4 nF. Measurement results demonstrate fast transient response on the order of nanoseconds. A peak efficiency of 76.1% is achieved, and the output voltage ripple is kept below 15 mV over the entire range of load current from 40 to 180 mA. [ABSTRACT FROM AUTHOR]

A low-power low-voltage CMOS receiver architecture with a combined LNA-VCO-mixer structure is proposed. An inversion-coefficient (IC) based design procedure is presented that facilitates finding a power-efficient operating point for the low-noise amplifier (LNA) and the voltage-controlled oscillator (VCO) blocks. At the architecture level, the bias currents of LNA and mixer are combined, filtered, and reused for the VCO. This approach facilitates lowering the supply voltage and improves the power efficiency of the system. As a proof of concept, a 2.4 GHz receiver suitable for wireless sensor network applications is designed and fabricated in a 0.13-µm CMOS process. The receiver has an intermediate frequency (IF) of 50 MHz. The RF-to-IF gain of the receiver is 30.1 dB and its noise figure (NF) is 8.3 dB. The combined LNA-VCO-mixer receiver consumes 510 µW from a 0.8-V supply. [ABSTRACT FROM AUTHOR]

Photonic networks form the backbone for data communications. In particular, in current and future wireless communication systems, photonic networks are becoming increasingly popular for data distribution between the central office and the remote antenna units at base stations. As wireless-photonic systems become in increasing demand, low-cost implementation of such systems will be desirable. This paper describes how integrated photonics and electronics, on silicon, can be used to design such systems. Various building blocks of such silicon-photonics systems are reviewed. The emphasis is on a 60 GHz wireless system which could be suitable for the emerging 5th-generation (5G) cellular networks. The implementation discussed here uses digital baseband optical transmission as opposed to the radio-over-fibre approach. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) is an emerging computing concept that describes a structure in which everyday physical objects, each provided with unique identifiers, are connected to the Internet without requiring human interaction. Long-term and self-sustainable operation are key components for realization of such a complex network, and entail energy-aware devices that are potentially capable of harvesting their required energy from ambient sources. Among different energy harvesting methods, such as vibration, light, and thermal energy extraction, wireless energy harvesting (WEH) has proven to be one of the most promising solutions by virtue of its simplicity, ease of implementation, and availability. In this article, we present an overview of enabling technologies for efficient WEH, analyze the lifetime of WEH-enabled IoT devices, and briefly study the future trends in the design of efficient WEH systems and research challenges that lie ahead. [ABSTRACT FROM PUBLISHER]

This paper presents a high-efficiency 60-GHz on–off keying (OOK) transmitter (TX) designed for wireless network-on-chip applications. Aiming at an intra-chip communication distance of 20 mm, the TX consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator. For high efficiency, a common-source topology with a drain-to-gate neutralization technique is chosen for the DA. A detailed mathematical design methodology is derived for the neutralization technique. The bulk-driven OOK modulator employs a novel dual feedthrough cancellation technique, resulting in a 30-dB on–off ratio. Fabricated in a 65-nm bulk CMOS process, the TX consumes only 19 mW from a 1-V supply, and occupies an active area of \ 0.077 mm^2. A maximum modulation data rate of 16 Gb/s with 0.75-dBm output power is demonstrated through measurements, which translates to a bit-energy efficiency of 1.2 pJ/bit. [ABSTRACT FROM AUTHOR]

Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc–dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver. [ABSTRACT FROM AUTHOR]

An introduction to the special issue on embedded signal processing circuits and systems for cognitive radio-based wireless communication devices, is presented.

A fully integrated 0.18 μm DC-DC buck converter using a low-swing "stacked driver" configuration is reported in this paper. A high switching frequency of 660 MHz reduces ifiter components to fit on chip, but this suffers from high switching losses. These losses are reduced using: 1) low-swing drivers; 2) supply stacking; and 3) introducing a charge transfer path to de- liver excess charge from the positive metal-oxide semiconductor drive chain to the load, thereby recycling the charge. The working prototype circuit converts 2.2 to 0.75-1.0 V at 40-55 mA. Design I and simulation of an improved circuit is also included that further improves the efficiency by enhancing the charge recycling path, providing automated zero voltage switching (ZVS) operation, and synchronizing the half-swing gating signals. [ABSTRACT FROM AUTHOR]