88 results on '"Mitsuyama, Yukio"'
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2. Radiation-Induced Soft Errors
3. Design Flow and Design Tools
4. Applications of Reconfigurable Processors as Embedded Automatons in the IoT Sensor Networks in Space
5. Radiation-Induced Soft Errors
6. NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode
7. A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling
8. Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation
9. Development of Autonomous Driving System based on Image Recognition using Programmable SoCs
10. Characterizing Energetic Dependence of Low-Energy Neutron-Induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65-nm Bulk SRAM
11. Impact of Neutron-induced SEU in FPGA CRAM on Image-based Lane Tracking for Autonomous Driving: from Bit Upset to SEFI and Erroneous Behavior
12. A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling
13. NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode
14. Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs
15. 33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications
16. Measurement of Variations in FPGAs under Various Load Conditions
17. Development of Autonomous Driving System Using Programmable SoCs
18. Impact of Neutron-Induced SEU in FPGA CRAM on Image-Based Lane Tracking for Autonomous Driving: From Bit Upset to SEFI and Erroneous Behavior.
19. Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars
20. Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture
21. Performance variation measurement on commercial FPGAs under various operating conditions
22. Novel processor architecture for onboard infrared sensors
23. A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch
24. Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis
25. Variability and Soft-Error Resilience in Dependable VLSI Platform
26. Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing
27. Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices
28. NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time
29. SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects
30. Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design
31. Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture
32. Reliability-configurable mixed-grained reconfigurable array supporting C-to-array mapping and its radiation testing
33. Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement
34. A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling
35. Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices
36. PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices
37. Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices
38. SET pulse-width measurement eliminating pulse-width modulation and within-die process variation effects
39. Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits
40. Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures
41. Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
42. Neutron induced single event multiple transients with voltage scaling and body biasing
43. Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
44. Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits
45. Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration
46. Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution
47. Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution
48. Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits
49. Alpha-particle-induced soft errors and multiple cell upsets in 65-nm 10T subthreshold SRAM
50. Soft error resilient VLSI architecture for signal processing
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