49 results on '"Miwa, Shinobu"'
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2. Evaluating architecture-level optimization in packet processing caches
3. Power Management Framework for Post-petascale Supercomputers
4. Analyzing the Performance Impact of HPC Workloads with Gramine+SGX on 3rd Generation Xeon Scalable Processors
5. Power Management Framework for Post-petascale Supercomputers
6. CNFET7
7. Analyzing Performance and Power-Efficiency Variations among NVIDIA GPUs
8. Three Quads: An Interconnection Network for Interactive Simulations
9. Performance estimation of high performance computing systems with Energy Efficient Ethernet technology
10. A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth
11. PredCom: A Predictive Approach to Collecting Approximated Communication Traces
12. RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache
13. Footprint-Based DIMM Hotplug
14. Evaluating the Impact of Energy Efficient Networks on HPC Workloads
15. Functionally-Predefined Kernel: a Way to Reduce CNN Computation
16. Multi-Level Packet Processing Caches
17. Data prediction for response flows in packet processing cache
18. Evaluation of Task Mapping on Multicore Neural Network Accelerators
19. Initial Study of Reconfigurable Neural Network Accelerators
20. A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip
21. Profile-based power shifting in interconnection networks with on/off links
22. Low-power cache memory with state-of-the-art STT-MRAM for high-performance processors
23. Runtime multi-optimizations for energy efficient on-chip interconnections1
24. Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches
25. Evaluation of Core Hopping on POWER7
26. Three Quads: An Interconnection Network for Interactive Simulations
27. Data-aware power management for periodic real-time systems with non-volatile memory
28. Design Aid of Multi-core Embedded Systems with Energy Model
29. Area-Efficient Microarchitecture for Reinforcement of Turbo Mode
30. Normally-off computing project: Challenges and opportunities
31. Integrating Multi-GPU Execution in an OpenACC Compiler
32. Performance modeling for designing NoC-based multiprocessors
33. Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping
34. Performance estimation of high performance computing systems with Energy Efficient Ethernet technology
35. Predict-More Router: A Low Latency NoC Router with More Route Predictions
36. D-MRAM Cache: Enhancing Energy Efficiency with 3T-1MTJ DRAM / MRAM Hybrid Memory
37. McRouter.
38. Stepwise sleep depth control for run-time leakage power saving
39. A novel power-gating scheme utilizing data retentiveness on caches
40. Communication Library to Overlap Computation and Communication for OpenCL Application
41. Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating
42. Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches
43. Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis
44. Parallelizing Hilbert-Huang Transform on a GPU
45. An Instruction Scheduler for Dynamic ALU Cascading Adoption
46. Optimal pipeline depth with pipeline stage unification adoption
47. D-MRAM cache.
48. McRouter: Multicast within a router for high performance network-on-chips.
49. Three Quads: An Interconnection Network for Interactive Simulations.
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