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This letter presents a differential transimpedance (TI) amplifier with a maximum gain of 71 dB $\Omega $ and a bandwidth (BW) of 65 GHz, including the effect of a photodetector with 65-fF capacitance. The implemented circuit in a 130-nm SiGe BiCMOS process with $f_{T}$ = 300 GHz has an averaged input-referred noise current of 7.2 pA $/\sqrt {\textrm {Hz}}$ , while the total harmonic distortion is better than 1.5% for peak-to-peak differential input currents lower than 0.8 mA at a differential output voltage of 0.8 V. Time-domain measurements show an open eye at 112 and 100 Gb/s for a non-return-to-zero and pulse-amplitude-modulation 4-level signals, respectively. The presented design, to the best of our knowledge, shows the lowest noise and one of the highest gain–bandwidth (GBW) products compared to the state-of-the-art. The improvement of the TI limit is achieved by optimizing the open-loop GBW product of the core amplifier in a shunt-feedback structure. This includes tradeoffs associated with the selection of a high value for the feedback resistor to keep the input-referred noise low. The BW is further increased by using a series inductor at the input and a T-coil at the output.

For delay-regulation purposes, delay-line based applications requiring data to be applied at the input can not use conventional delay-locked-loops (DLLs), which necessitate the reference clock to be applied at the input of the delay-line. This brief presents a DLL which uses a part of the data delay-line, referred to as replica delay-line, to match the delay of the data delay-line to the input clock period. The DLL performs this delay-regulation by setting the current ratio in its charge pump to a particular ratio defined by the delay-elements in the data and the replica delay-line. Designed in 45-nm SOI CMOS, the 4-tapped differential replica delay-line based DLL (R-DLL) is demonstrated to regulate the delay of the tunable data delay-line to within one least significant bit (LSB) delay-lock error for the input clock frequencies ranging from record 0.77-5 GHz. The R-DLL consumes only 17 mW of power and 0.009 mm2 of area, while enabling the 32-tapped 25 Gb/s differential data delay-line to achieve a lock range $2.3\times $ better than reported in literature.

This paper studies the design and measurement of a PAM-8 modulator driver based on a 3-bit digital-to-analog converter (DAC) architecture in a 130-nm SiGe BiCMOS process. The driver is implemented as a two-stage topology. The first stage consists of three single-ended to differential converters (SDC) and the second stage includes the DAC core. The driver has an output voltage swing of 4 V pp.ditf , thus enabling high extinction ratios when implemented in an electro-optical transmitter. It reaches a symbol rate of 50 Gbaud and consumes 590 mW of DC power, therefore being one of the most power efficient drivers reported in the literature.

An 80-Gb/s $2^{15}-1$ pseudorandom binary sequence (PRBS) generator suitable for testing binary communication systems is presented. Implemented in a 130-nm SiGe process, the circuit is optimized for low power dissipation. For the core functionality, an energy efficiency of 1 pJ/bit is achieved, which is one of the best values among comparable published designs. In addition, the improvement of the output signal in time domain and frequency domain is targeted. The key factors affecting an ideal PRBS spectrum are identified and addressed from the system and circuit point of view. This results in spur suppression of higher than 40 dB, which is 15 dB better than previously reported works exceeding 40 Gb/s. As an output driver, a modified Cherry–Hooper amplifier is chosen. A parametrized design methodology for obtaining Bessel response is introduced and the amplifier is optimized for low power operation. Measurement results show a single-ended output signal with over 300-mV eye opening, 0.6-ps rms jitter, and a signal-to-noise ratio better than 10.5 at 80 Gb/s, which is the best-in-class output eye diagram for a PRBS generator, to the best of our knowledge.

This brief presents a 4-bit digitally controlled differential delay element (DCDE) with high-speed and high-resolution capability, two challenging requirements in the design of delay elements. Two input bits, inside the differential current-mode logic (CML) DCDE, regulate its bias current and the resistive load, while the other two bits configure the output capacitive load enabling the presented DCDE to achieve a phase shift of 20 ps and an average resolution of 1.25 ps. Designed in 45-nm silicon-on-insulator (SOI) CMOS, the DCDE dissipates 4 mW of power under maximum biasing condition and can operate up to 10 Gb/s while adding only 0.6 ps of root-mean-square jitter to the delayed input. To the best of authors knowledge, the designed DCDE is the first 4-bit low-jitter 10-Gb/s variable-load CML DCDE offering a time resolution of 1.25 ps, making it a suitable candidate for high-speed and high-resolution applications.

An integrated generator for 3-bit pulse amplitude modulation (PAM-8) is presented, supporting symbol rates above 30-GBaud. To optimize the generated pulses for a transmission, the digital input word is mapped to the binary-weighted segments of a digital-to-analog converter using the binary reflected Gray code, which minimizes the total bit error probability. The mapping is realized using full-rate digital logic based on exclusive-or gates. For validation, the circuit was fabricated in a 130-nm SiGe BiCMOS technology and measured on a PCB in combination with three pseudo-random bit sequence generators. At a symbol rate of 33.4-GBaud, the circuit can generate Gray-coded signals at 100.2-Gbit/s with PAM-8 and 66.8-Gbit/s with PAM-4.

This letter presents the design and measurements of a monolithically integrated photonic receiver manufactured in 0.25 μm SiGe BiCMOS electro-photonic technology. The receiver consists of an on-chip germanium photodiode directly connected to the transimpedance amplifier (TIA). An on-chip, low-noise feedback loop compensates the dc photocurrent. The circuit provides a maximum bandwidth of 35.6 GHz at a gain of 59.2 dBQ with a noise of 12.34 pA/√(Hz) while consuming only 80 mW. In combination with a 20 GHz, 1550 nm electro-optical transmitter, a maximum data rate of 50 Gb/s at a bit error rate of less than 10 -12 was measured. To the best of the authors' knowledge, this is the fastest error-free detected data rate reported for a monolithically integrated photonic receiver. Additionally, the feedback resistor of the TIA can be tuned via a MOSFET allowing error-free operation at 20 Gb/s with a sensitivity of only -13 dBm. In this setting the input-referred noise is only 8.16 pA/√(Hz).

This paper presents a time-to-digital converter-based oversampling input-delayed multi-standard adaptable data-receiver architecture which digitizes transitions/threshold-crossings and inter-transition distances inside a time-varying binary input symbol sequence. The presented circuit works by sampling delayed replicas of a threshold-crossing binary input symbol sequence inside a differential delay-line. The resulting sampled digital word carries information of the threshold-crossings and the distances between them. The proposed 64-tapped adaptable-delay-line-based design is intended as a high-rate oversampling baseband binary quantizer for a high-speed serial link. The data-receiver has been demonstrated to digitize up to 25-Gb/s input binary symbol sequences with an oversampling ratio of eight. Designed in a 45-nm SOI CMOS process, the receiver circuit is fully characterized by applying different symbol sequences at its input while setting its time resolution and dynamic-range/delay to 5 and 320 ps, respectively. Under these conditions, the data-receiver consumes 270 mW of power, and achieves an energy conversion figure of 1.62–4.32 pJ/sampled-digital-bit. The circuit occupies 0.24 mm2 of active silicon area. The proposed receiver offers one of the highest time-resolution and oversampling factor, and among the best energy conversion figures compared with the oversampling time-mode receiver architectures reported so far.

This paper presents a high-swing vertical-cavity surface-emitting laser (VCSEL) driver with two-tap feed-forward equalizer (FFE) in 14-nm FinFET CMOS technology. The design features a standby mode with power-ON time below 10 ns and 86% of power saving. Based on system-level simulations, the impact of the driver swing, tap delay, and weight on the optical eye-opening is studied and it is shown that the FFE combined with high-swing driving can improve the output eye at rates beyond two times the bandwidth of the VCSEL. By applying an extra supply, the output stage is optimized to provide high swing (0.65 V) without suffering from the slow response of a transistor in the triode region. In addition, the bias and modulation currents can be adjusted to accommodate different VCSELs. The designed circuit is tested with two VCSEL types. It is bonded to common-cathode 20 and 18 GHz VCSELs, and in both the cases, data transmission at 45 Gb/s with bit error rate lower than 10−12 is measured. The total power dissipation is below 100 mW, providing a power efficiency of better than 2.11 pJ/bit. To the best of our knowledge, this design is the fastest VCSEL driver in any CMOS technology, which is also capable of burst mode operation.

A unique pulsewidth modulation (PWM) architecture is presented which works by controlling the discharge rate of a capacitor. The designed PWM modulator consists primarily of a 2-bit current-steering digital-to-analog converter (DAC) and a voltage-to-time converter (VTC). The VTC operates in two phases. The first phase requires the capacitor to be charged to the supply rail, while the second phase discharges the capacitor using the control voltage generated by the DAC. The rate of the capacitor discharge defines the width of the output PWM pulse. The proposed PWM modulator, implemented in 45-nm silicon-on-insulator CMOS, occupies an active silicon area of $30\times 120\,\,\mu \text{m}\,\,{^{\mathrm{ 2}}}$ , achieves data rates upto 10 Gb/s and dissipates only 9 mW of total power. To the best of the authors’ knowledge, the proposed PWM modulator achieves the best energy per bit figure and is the most power area efficient reported to date.

In this paper we introduce the design of a 2.5GHz low power CMOS inverter based 4-bit programmable delay cell with high linearity. The circuit is designed and optimized for the use in high-speed current-steering digital-to-analog converters. The basic architecture consists of a current-starved CMOS inverter delay element and a linear 4-bit digital-to-analog converter providing the reference current for the delay element. In addition, an analog low power pre-distortion circuit has been implemented which is modulating the output current of the DAC to compensate for the inherent nonlinearity of the delay element. Thus, the major drawback of state-of-the-art low power CMOS inverter based delay elements has been significantly mitigated whereas the power consumption is still 25 times less than for shunt-capacitor based architectures with comparable linearity. The delay cell including reference current generation and pre-distortion of the reference current only consumes 90 $\mu W$ and is therefore well suited for low power applications. The proposed delay cell is implemented along with a CMOS pseudo-random bit sequence (PRBS) generator and a retiming flip-flop for providing a test data sequence at the input. Furthermore, a ${(50 \Omega)}$ impedance matched buffer circuit has been implemented to measure the exact undistorted waveforms of the delay element at the output. The system is implemented and fabricated in a 22nm FD-SOI CMOS process.

This paper presents the design and characterization of a new delay-line based demultiplexer (Demux). The Demux works by setting the delay of each delay-element in the delay-line equal to the period of the input symbol and the delay of the delay-line equal to the period of the sampling clock. Once the delay-line is sampled, each sampled output represents a unique symbol in the input symbol sequence. As opposed to the traditional tree-architecture Demux, the proposed delay-line Demux dissipates power only in the delay-line. In addition to design simplicity, the delay-line Demux also offers power and area advantages over tree Demux when scaled to a higher channel count. Designed in 45-nm RFSOI CMOS, the Demux achieves 2.6 pJ/symbol of energy figure, which, to the best of the authors knowledge, is the best reported among inductor-less CMOS Demuxes.

This paper presents the design and characterization of a unique low-power pulsewidth demodulator (PWDM) which works by controlling the total amount of charge stored on a capacitor. The proposed PWDM consists of a time-to-voltage converter (TVC) and a flash architecture based 2-bit analog-to-digital converter (ADC). The TVC operates in two phases: the charge phase and the discharge phase. During the charge phase an input pulsewidth-modulated (PWM) signal charges a capacitor to a certain value. The larger the width of the PWM signal, the higher the voltage developed across the charged capacitor. This capacitor voltage, which is unique to each pulsewidth, is then digitized inside a 2-bit ADC. During the discharge phase, the capacitor is allowed to completely discharge to ground. Designed in the 45-nm RFSOI CMOS, the PWDM occupies an active area of 70 × 80 µm2, achieves data rates upto 8 Gb/s, and dissipates only 7.25 mW of power. To the best of the authors' knowledge, the proposed PWDM offers the best energy figure compared to the existing pulsewidth demodulator designs.

This paper presents the design and characterization of a low output jitter and high resolution pulsewidth modulator in 45-nm SOI CMOS. The modulator uses a current mode logic (CML) delay line to generate delayed phases of a reference signal. A digital input vector selects a particular delayed phase inside a CML phase selector. The delayed and undelayed phases of the reference are then combined inside a CML OR gate to generate different pulsewidths. The designed 2-bit 10 Gb/s CML pulsewidth modulator offers the highest time resolution of 10 ps, least output jitter of 0.6 ps, and among the best energy figures of 2.8 p.J/bit in comparison to the reported pulsewidth modulators.

This paper presents the design and characterization of a low power 20 Gb/s 1:4 demultiplexer (Demux) in 45-nm SOI CMOS. For the design of the latch, which is used primarily inside the key building blocks of the 1:4 Demux, a power-speed optimized current-scaling methodology is provided. The results of an electromagnetic (EM) 3D field solver, which was used to simulate the high-frequency performance of the most critical data and clock paths inside the Demux, are presented. The designed 1:4 Demux uses a supply voltage of 1 V, dissipates a total of 77 mW of power, and occupies an active area of 0.122mm2. Among the reported inductorless CMOS 20 Gb/s 1:4 Demuxes, the presented Demux achieves the best energy figure of 3.8 pJ/bit.

This paper reports on a cross-coupled latch-based static clock divider circuit with a wide frequency division range. Detailed circuit level design for wideband operation of the clock divider is discussed and insightful measurement results are reported. These include output divided clock power levels, output clock jitter, eye diagrams, and the sensitivity plot of the clock divider. Designed in 45-nm CMOS, the clock divider is measured to have a frequency division range of 1–60 GHz, moderate power consumption of 9.6 mW and among the best energy figures compared to the reported clock dividers.

This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of ${\hbox{0.12 mm}}^{2}$ . Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving.

This brief presents a 25-GS/s track-and-hold amplifier (THA) implemented in a 28-nm low-power digital CMOS process. Given the intrinsic low-pass behavior of the THA core, a frequency compensation technique is employed to improve the bandwidth by increasing the input amplitude for higher frequencies. This enhances the small-signal bandwidth by almost 30% to 70 GHz. Large-signal measurements show a 3-dB corner frequency of 55 GHz, which enables a performance sufficient for time-interleaved analog-to-digital converter systems operating above 100 GS/s. At a peak-to-peak input amplitude of 400 mV, the total harmonic distortion is −32 dB for a 50-GHz input signal at a dc power consumption of 73 mW.

This paper presents a comparison of passive and active differential-mode delay-line structures. Active delay elements with and without bandwidth extension are considered for comparison. The key comparison metrics include delay-tunablity, signal integrity at the output of the delay-line, tapper-factor, bandwidth, group delay variations and the area consumption. Conforming to the presented comparison, a high tapper-factor, wideband and delay-tunable delay-line topology is selected and characterized in 45-nm CMOS process.