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Approximate matrix inversion based methods is widely used for linear massive multiple-input multiple-output (MIMO) received symbol vector detection. Such detectors typically utilize the diagonally dominant channel matrix of a massive MIMO system. Instead of diagonal matrix, a stair matrix can be utilized to improve the error-rate performance of a massive MIMO detector. In this paper, we present very large-scale integration (VLSI) architecture and field programmable gate array (FPGA) implementation of a stair matrix based iterative detection algorithm. The architecture supports a base station with 128 antennas, 8 users with single antenna, and 256 quadrature amplitude modulation (QAM). The stair matrix based detector can deliver a 142.34 Mbps data rate and reach a clock frequency of 258 MHz in a Xilinx Virtex -7FPGA. The detector provides superior error-rate performance and higher scaled throughput than most contemporary massive MIMO detectors.

Massive multiple-input multiple-output (MIMO) is a key technology for fifth generation (5G) communication system. MIMO symbol detection is one of the most computationally intensive tasks for a massive MIMO baseband receiver. In this paper, we analyze matrix decomposition algorithms for massive MIMO systems, which were traditionally used for small-scale MIMO detection due to their numerical stability and modular design. We present the computational complexity of linear detection mechanisms based on QR, Cholesky and LDL-decomposition algorithms for different massive MIMO configurations. We compare them with the state-of-art approximate inversion-based massive MIMO detection methods. The results provide important insights for system and very large-scale integration (VLSI) designers to select appropriate massive MIMO detection algorithms according to their requirement., Comment: 6 pages, 7 figures, accepted in NORCAS 2020