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This work presents a 25 MHz adaptive on/off-time-controlled three-level buck converter with a fast reference tracking speed and high light load efficiency. The self-balancing scheme of the flying capacitor voltage is revised and extended for a broad conversion ratio range from 0.17 to 0.833. To reduce the error of the self-balancing scheme when applied to a high frequency three-level buck converter with an on-chip flying capacitor, a real-time calibration loop on the flying capacitor voltage is introduced, effectively reducing the balancing error from 340 mV to 20 mV. A turning-point output voltage prediction for the three-level buck converter is presented to achieve near-optimal reference tracking with a fast tracking speed and negligible output voltage undershoot or overshoot. The up- and down-tracking takes 81 ns and 72 ns, respectively, for a 1-V step with an inductor of 47 nH and an output capacitor of 47 nF. The three-level converter achieves a precise discontinuous conduction mode (DCM) operation with an adaptive switching frequency at light load by means of a feedback loop-based method. An approximately 28.2% increment in efficiency is achieved with a load of 10 mA. The three-level buck converter has a peak efficiency of 92.8% and an over 85% efficiency in most of the operation regions. [ABSTRACT FROM AUTHOR]

This paper presents a turning-point output voltage (TPOV) prediction method to enhance the reference tracking speed of buck converters for dynamic voltage and frequency scaling (DVFS) application. The optimal reference tracking is modeled, and the TPOV is formulated. The parasitic effects are compensated with the proposed calibration scheme. Reference tracking considering load current changes is evaluated with the proposed end-point determination method. Additionally, this work optimizes the feedback network for smooth loop transition, and incorporates the frequency-locking circuit and the error correction path to address the shortcomings of the hysteretic control. The prototype is fabricated in a 0.13- $\mu \text{m}$ CMOS process with a 1.2-V supply voltage. The converter achieves a near-optimum reference tracking over a wide range of output voltages, from 0.5 to 1 V. Various output voltage steps are measured for different load cases. For a 0.5–1-V output voltage step, with a 90-nH inductor and a 1- $\mu \text{F}$ output capacitor, the up- and down-tracking take 558 and 542 ns, respectively, matching the theoretical result of 533 ns. The prototype achieves a peak efficiency of 93.5%, and over 85% efficiency is measured with $\mathrm {V}_{\mathrm {O}}$ from 0.5 to 1 V and $\mathrm {I}_{\mathrm {O}}$ from 130 to 550 mA. [ABSTRACT FROM AUTHOR]

This paper presents a systematic analysis of integrated 3-level buck converters under both ideal and real conditions as a guidance for designing robust and fast 3-level buck converters. Under ideal conditions, the voltage conversion ratio, the output voltage ripple and, in particular, the system's loop-gain function are derived. Design considerations for real circuitry implementations of an integrated 3-level converter, such as the implementation of the flying capacitor, the impacts of the parasitic capacitors of the flying capacitor and the 4 power switches, and the time mismatch between the 2 duty-cycle signals are thoroughly discussed. Under these conditions, the voltage conversion ratio, the voltage across the flying capacitor and the power efficiency are analyzed and verified with Cadence simulation results. The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method. The derived loop-gain functions are verified with time-domain small signal injection simulation and measurement, with a good match between the analytical and experimental results. [ABSTRACT FROM AUTHOR]

A new gate drive circuit to reduce the power loss and switching noise of single-inductor-multiple-output regulators is presented. Efficiency degradation and switching noise induced by the cross-talk of the voltages and currents within the power stage and buffer are analyzed. A shoot-through-current (STC) controlled buffer with four-transistor (4T) inverters is presented, and the 4T inverter enables internal STC control and generates two outputs with dead-time. To further isolate the cross-talk, two separate high voltage selectors (HVS) with the proposed buffer are used to power the buffer and the power P-MOSFET body, respectively. Simulation results show that the peak and average currents of the proposed buffer are smaller and much less sensitive to the buffer size than those of the traditional inverter based buffer. Two single-inductor-dual-output boost converters with and without the proposed techniques have been fabricated in a 0.35-\mum CMOS process. Experimental results show that the maximum efficiency is increased from 87.8% to 91.6% with the proposed technique. [ABSTRACT FROM PUBLISHER]

Conventionally, inductor current is sensed and quantized before it can be used by digitally controlled DC-DC converters. These are intuitively done by using two separated functional blocks—an analog current sensor and an ADC. A few research works have investigated other ways of obtaining the inductor current information in the digital domain. This paper proposes an on-chip digital inductor current sensor that combines both the inductor current-sensing and quantization into a single functional block. In this way, the redundancies found in the conventional approach can be reduced and optimizations can be made to save chip area and power consumption. An 8-bit digital inductor current sensor has been designed and fabricated with a UMC 0.13~\mum CMOS process. The measurement results show that the digital sensor can provide digital inductor current information with a conversion time of 225 ns. This can be used by a buck converter with a switching frequency up to 4 MHz. The digital sensor has linear and monotonic input-output transfer curve properties with an LSB of 6.79 mA. It consumes current of 700~\muA at 1.2 V supply voltage. [ABSTRACT FROM PUBLISHER]

An output voltage ripple aware design of different voltage ramp signal of voltage-mode CCM random frequency buck converter for conductive EMI reduction is presented. A mathematical analysis has been carried out to model the output voltage ripple of random switching converter. Simulations of the converter have been undertaken and measured results from the converter fabricated with a standard 0.35 \mum CMOS process verify the proposed design approach. From experimental results, a carefully designed ramp can reduce the output voltage ripple by more than 8 times without significant influence on the inductor current spectrum spread and any increment on the output filtering inductance and capacitance comparing to the conventional design. [ABSTRACT FROM AUTHOR]

Digital current-mode control is a dual-loop control which potentially results in a better transient response and thus is more favorable than voltage-mode control. There are only a few publications on how to design and implement a fully integrated digital controller as the on-chip implementation is very challenging, especially for current-mode control. This paper addresses those design challenges and considerations. One of the main challenges is to efficiently sample and quantize both the output voltage and inductor current of the buck converter for control purposes. A time-multiplex scheme is used for the control-loop which enables the converter to work with a single ADC. A modified delay-lock-loop DPWM has been developed for minimizing the mismatch of the delay-cells. This enhances the accuracy at high frequency to prevent limit-cycle. A new algorithm has also been proposed for implementing look-up-table digital compensators with 20% less chip area. A converter with the fully integrated digitally controlled loop, including the single ADC, digital compensators and DPWM, has been fabricated in a CMOS 0.35 \mum process with a chip area of 1049 \mum \times\,1533 \mum. Measurement results show that the buck converter has a load transient response of 20 \mus, which is one of the fastest compared to other state-of-the-art digitally controlled buck converter. [ABSTRACT FROM PUBLISHER]

This paper analyzes the dynamics of reference tracking in switched-mode power converters in terms of both large-signal and small-signal perspectives. Common control schemes, namely, voltage mode, current mode, and V^2-control, are compared for their performance in reference tracking. For small-signal analysis, loop gains and reference-to-output transfer functions are analytically derived and verified by the proposed Matlab-based frequency response simulator. In the case of multiple-loop control like V^2-control, different loop gains are clarified for their application in load transient or reference tracking. Practical circuit-level design considerations are given to current-mode control for achieving fast reference tracking, while end-point prediction (EPP) is used to improve V^2-control, which is inherently slow in reference tracking. The effect of EPP on transfer function is then explained in details. A V^2-controlled buck converter with EPP is fabricated. The measured reference-tracking response shows ten times improvement in tracking speed and verifies the effectiveness of EPP in V^2-control. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power stability strategy to significantly reduce the power consumption of a three-stage amplifier using active-feedback frequency compensation (AFFC). The bandwidth of the amplifier can also be enhanced. Simulation results verify that the power dissipation of the AFFC amplifier is reduced by 43% and the bandwidth Is Improved by 32.5% by using the proposed stability strategy. In addition, a dynamic feedforward stage (DFS), which can be embedded into the AFFC amplifier to improve the transient responses without consuming extra power, is proposed. Implemented in a 0.6-μm CMOS process, experimental results show that both AFFC amplifiers with and without DFS achieve almost the same small-signal performances while the amplifier with DFS improves both the negative slew rate and negative 1% settling time by two times. [ABSTRACT FROM AUTHOR]

This paper presents a rigorous transfer function analysis of the power supply rejection ratio (PSRR) of low-dropout (LDO) regulators and the LDO with the feed-forward ripple cancellation (FFRC) scheme. Four main noise sources of conventional LDOs are first clarified. An efficient and accurate model is proposed to facilitate the analysis, and the transfer function, along with the poles and zeros, is derived based on the simplified model. Software simulation results and numerical plots are both demonstrated and compared to verify the analytical results, with respect to two specific design examples. The widely-used FFRC scheme for PSRR enhancement is also reinvestigated based on the proposed model. With the inclusion of the FFRC circuit, the new transfer function with new poles and zeros is presented. The working principles of the FFRC scheme are illustrated and the optimal FFRC case is clarified. The proposed model and the derived transfer function match well with the simulation results and the measurement results in prior works. The proposed model and the analytical results serve as the theoretical foundation of the design of high-PSRR LDOs. The recommended simulation methodology could be helpful during the circuit design phase. [ABSTRACT FROM AUTHOR]

This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near- $V_{{\text {DD}}}$ negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the high dv / dt slew rate of $V_{\text {X}}$ when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of $V_{\text {X}}$ , thus the near-optimal zero-voltage switching can be achieved with deviation < 3 ns. The GaN driver is implemented with a 0.18- $\mu \text{m}$ BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a novel thermoelectric energy harvesting system with a reconfigurable array of thermoelectric generators (TEGs), which requires neither an inductor nor a flying capacitor, is proposed. The proposed architecture can accomplish maximum power point tracking (MPPT) and voltage conversion simultaneously via the reconfiguration of the TEG array, and demonstrate significantly improved power conversion efficiency over the conventional switching converter and switched-capacitor architectures. Two systematical scaling approaches—powers-of-two scaling and maximum-factor scaling—are presented and analyzed to serve as the design guideline, catering for reconfigurable TEG arrays of different sizes. In order to optimize the chip area required, a custom-designed, multi-level hierarchy and systematically scalable switch array that requires a reasonable number of switches is also developed to enable the reconfiguration of the TEG array. The 16-node and 12-node versions of the proposed system have been implemented in a standard 0.35- \mu \textm CMOS process. Measurement results verify the analysis, and confirm that the proposed system can maintain a higher than 88.8% efficiency over a wide range of temperature gradients. [ABSTRACT FROM PUBLISHER]

This paper introduces an on-chip distributed power delivery grid (DPDG) with cooperative regulation and IR-drop reduction based on analog-assisted digital LDOs (AADLDOs), which inherit the merits of low output ripple and sub-LSB current supply ability from the analog control, and the advantage of low supply voltage operation and adaptive fast response from the digital control. With the distributed power delivery topology, the IR-drop across the power supply rail can be reduced, especially in large area power-supply applications. The AADLDOs in the power delivery grid work cooperatively to obtain a balance between improved response speed and power consumption. A prototype of a 3 × 3 power grid with 9 AADLDOs, providing a total of 500-mA maximum load current with an on-chip 0.9-nF output capacitor, is fabricated in a 65-nm CMOS process to demonstrate the proposed DPDG concept and the effectiveness of this scheme. A maximum voltage undershoot of 125mV is measured with a 450mA/20ns load step, resulting a figure-of-merit as low as 0.249ps. [ABSTRACT FROM AUTHOR]

A circuit-oriented geometrical approach in predicting subharmonic oscillation (SHO) of voltage-mode switching converters is presented. It is based on a straightforward graphical analysis of the operation of the converter without using advanced mathematical techniques. It is shown that the slope of the output of the compensator at the trip point is an important factor in determining the onset of SHO. The critical condition of SHO of the buck converter working in continuous conduction mode (CCM) is derived and expressed in terms of circuit parameters that serve as the design guideline for avoiding SHO. The proposed approach is applied to analyze three schemes, namely, proportional, dominant-pole and Type-III compensation. The analysis of SHO in discontinuous conduction mode (DCM) for both the buck and the boost converters are also included to demonstrate the universality of the proposed approach. Crucial Cadence simulation results and measurement results are presented to verify the analysis. [ABSTRACT FROM AUTHOR]

The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35-μm CMOS technology. It is proven experimentally that the LDO provides stable voltage regulation at a variety of output-capacitor/ESR conditions and is also stable in no output capacitor condition. The preset output voltage, minimum unregulated input voltage, maximum output current at a dropout voltage of 200 mV, ground current and active chip area are 1 V, 1.2 V, 50 μA, 95 μA, and 140 μm × × 320 μm, respectively. The full-load transient response in the no output capacitor case is faster than a micro second and is about 300 ns. [ABSTRACT FROM AUTHOR]