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A class‐AB OTA (operational transconductance amplifier) topology with rail‐to‐rail input common‐mode range is proposed for application in very low‐voltage applications. High efficiency is achieved by reusing transistors both for class‐AB operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply voltages less than two threshold voltages. Simulations in 40 nm CMOS technology show 41 dB gain at ±0.3 V supply voltage, a unity‐gain frequency of 8.8 MHz on a 5 pF load, class‐AB behaviour and full rail‐to‐rail operation when closed in unity‐gain buffer configuration. [ABSTRACT FROM AUTHOR]

Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal‐to‐noise‐and‐distortion ratio (SNDR): CMOS switch non‐idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource‐consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10–24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and out‐of‐sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB. [ABSTRACT FROM AUTHOR]

A class-AB OTA (operational transconductance amplifier) topology with rail-to-rail input common-mode range is proposed for application in very low-voltage applications. High efficiency is achieved by reusing transistors both for class-AB operation and for mirroring the output currents, and a threshold lowering technique is applied to allow supply voltages less than two threshold voltages. Simulations in 40 nm CMOS technology show 41 dB gain at ±0.3 V supply voltage, a unity-gain frequency of 8.8 MHz on a 5 pF load, class-AB behaviour and full rail-to-rail operation when closed in unity-gain buffer configuration. [ABSTRACT FROM AUTHOR]

A Volterra model is used to calibrate a pipeline ADC simulated in Cadence Virtuoso using the STMicroelectronics CMOS 45 nm process. The ADC was designed to work at 50 MSps, but it is simulated at up to 125 MSps, proving that calibration using a Volterra model can significantly increase sampling frequency. Equivalent number of bits (ENOB) improves by 1-2.5 bits (6-15 dB) with 37-101 model parameters. The complexity of the calibration algorithm is reduced using different lengths for each Volterra kernels and performing iterative pruning. System identification is performed by least squares techniques with a set of sinusoids at different frequencies spanning the whole Nyquist band. A comparison with simplified Volterra models proposed in the literature shows better performance for the pruned Volterra model with comparable complexity, improving linearity by as much as 1.5 bits more than the other techniques. [ABSTRACT FROM AUTHOR]

A Volterra model is used to calibrate a pipeline ADC simulated in Cadence Virtuoso using the STMicroelectronics CMOS 45 nm process. The ADC was designed to work at 50 MSps, but it is simulated at up to 125 MSps, proving that calibration using a Volterra model can significantly increase sampling frequency. Equivalent number of bits (ENOB) improves by 1–2.5 bits (6–15 dB) with 37–101 model parameters. The complexity of the calibration algorithm is reduced using different lengths for each Volterra kernels and performing iterative pruning. System identification is performed by least squares techniques with a set of sinusoids at different frequencies spanning the whole Nyquist band. A comparison with simplified Volterra models proposed in the literature shows better performance for the pruned Volterra model with comparable complexity, improving linearity by as much as 1.5 bits more than the other techniques. [ABSTRACT FROM AUTHOR]

Switched capacitor sample and hold (SHA) stages in deep submicron technologies can achieve hundreds of mega samples per second of sampling frequency, but are affected by several nonlinear effects which reduce their signal-to-noise-and-distortion ratio (SNDR): CMOS switch non-idealities, amplifier nonlinearity, and incomplete settling. It is possible to model and correct distortions using Volterra kernels, which can be rather resource-consuming as the number of parameters to estimate rapid increases with the order and length of the kernels. In this reported work, it is shown that a switched capacitor SHA, simulated using the 45 nm process by STMicroelectronics, can be calibrated to achieve a 10-24 dB improvement in SNDR. Computational costs are kept low using a different lag value for each kernel, and iteratively pruning the elements of the Volterra kernels which affect linearity the least. A technique for estimation and outof- sample validation is presented and robustness checks are performed. A performance gain of 8.5 dB can be achieved with as few as 17 correction parameters, while 21 coefficients are enough to gain 12.2 dB, and 36 to gain 18.4 dB. [ABSTRACT FROM AUTHOR]

A biasing technique for minimum supply CMOS amplifiers is proposed. The bulk terminals of the input transistors of a pseudo-differential amplifier are exploited in a switched-capacitor control loop to set the quiescent current. Simulations on a design powered with 0.7 V show that the performance obtained is comparable to that of a traditional differential pair supplied with 1 V. [ABSTRACT FROM AUTHOR]

We present a low voltage low power architecture for an integrated current conveyor (CCII) topology, designed to decrease the stand-by power dissipation without affecting the CCII transient performance. In the proposed circuit, implemented in a standard AMS 0.35 um CMOS technology, an extra current flows into the circuit only when an input voltage variation occurs (through the adaptive biasing technique), so improving the transient response speed without a substantial increase of the average power consumption. Simulation results confirm the expected theoretical considerations. [ABSTRACT FROM AUTHOR]