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[ES] El objetivo del presente trabajo es adaptar un core IP de un microprocesador RISC-V segmentado para que pueda ser usado en sistemas SOC basados en buses Avalon. El core IP adaptado implementa una arquitectura RISC-V segmentada con soporte parcial del juego de instrucciones (ISA) RV32IM, y está desarrollado completamente en System Verilog. La característica principal de esta implementación es el uso de una arquitectura abierta y su bajo consumo. Lo que permitiría su uso en sistemas SOC desarrollados sobre dispositivos FPGA de bajo coste. El objetivo principal de este proyecto es diseñar y verificar nuevos módulos para la adaptación del microprpocesador al estándar de bus Avalon y su integración en el entorno de desarrollo de sistemas SOC de Intel FPGA Platform Designer. El resultado del trabajo permitirá crear sistemas SOC donde el microprocesador es interconectado con diferentes periféricos de forma sencilla a través de la herramienta Platform Designer , para lo cual será también necesario el desarrollo de un software y un hardware que permita realizar la programación, el control y la depuración del microprocesador desde un sistema externo., [EN] The objective of this work is to adapt a core IP of a segmented RISC­V microprocessor to be used in SOC systems based on Avalon buses. The adapted core IP implements a segmented RISC­V architecture with partial support to the (ISA) RV32IM instruction set, and it is completely developed on System Verilog. The main characteristic of this implementation is the usage of an open architecture and its low consume¿ this would allow its use in SOC systems developed over low­cost FPGA devices. The main objective of this project is to design and verify new modules to adapt the microprocessor to an Avalon bus standard and its integration in a SOC systems development environment of Intel FPGA PlatformDesigner. The result of this work would allow to create SOC systems where the microprocessor is interconnected with different peripherals easily through the Platform Designer tool, for which is also needed the development of a software and hardware to allow to program, to control and to debug the microprocessor from an external device.

[ES] En el presente trabajo, se parte de los resultados de un proyecto anterior, en el cual se desarrolló en Unity un sistema de realidad virtual para rehabilitación motora, centrado en la parte de entrenamiento. El presente proyecto complementa al anterior añadiendo al sistema las tareas de gestión que debe llevar a cabo el terapeuta. Los objetivos que se plantean son: (1) Generar un módulo que permita al terapeuta definir protocolos y ejercicios de entrenamiento de forma intuitiva, amigable y compatible con los formatos de entrada de la aplicación ya desarrollada. (2) Desarrollar un módulo de evaluación, que permita al terapeuta disponer de información sobre la correcta realización de los ejercicios por parte del paciente.

[ES] El presente Trabajo Fin de Máster ha sido desarrollado dentro de la empresa Maxlinear. Su objetivo principal es desarrollar una metodología que permita el uso del lenguaje de programación Python en un entorno de verificación UVM. Esto posibilita la creación de un conjunto de scripts de Python para la verificación ASIC en un entorno UVM, que posteriormente serán utilizados en un entorno de pruebas real, usando los mismos tests de verificación sobre el ASIC a nivel RTL y sobre el ASIC ya construido. Esta metodología se ha desarrollado con el objetivo de verificar el ASIC, una vez fabricado, en el menor tiempo posible. La verificación en un entorno UVM aporta un mayor control en la generación de situaciones de test y en la comprobación automática del correcto funcionamiento de todas las señales del ASIC. Además, la metodología propuesta en el presente TFM permite verificar los propios scripts de Python antes de ser usados en un entorno de pruebas real. Esto facilita la verificación del entorno de pruebas antes de la fabricación del chip, eliminando la necesidad de una implementación y verificación en FPGA, verificación que es lenta y, a veces, incompatible con determinados diseños. Para llevar a cabo esta nueva metodología, es necesario exportar una serie de funciones o tasks definidas en SystemVerilog a Python. Para ello, se ha utilizado la interfaz DPI (Direct Programming Interface) entre SystemVerilog y el lenguaje C, que permite llamar funciones de C desde SystemVerilog y exportar otras desde SystemVerilog para que sean llamadas desde C. Posteriormente, mediante la herramienta SWIG (Simplified Wrapper and Interface Generator), se generará un banco de pruebas en Python que permitirá acceder a las funciones generadas en C que se comunican con el banco de pruebas en UVM o con el banco de pruebas físico., [EN] This Master's Thesis has been developed within the company Maxlinear. Its main objective is to develop a methodology that allows the use of the Python programming language in a UVM verification environment. This enables the creation of a set of Python scripts for ASIC verification in a UVM environment, which will later be used in a real test environment, using the same verification tests on the ASIC at RTL level and on the ASIC already built. This methodology has been developed with the objective of verifying the ASIC, once built, in the shortest possible time. The verification in a UVM environment provides greater control in the generation of test situations and in the automatic verification of the correct operation of all the ASIC signals. In addition, the methodology proposed in this Thesis allows to verify the Python scripts themselves before being used in a real test environment. This facilitates the verification of the test environment prior to chip fabrication, eliminating the need for FPGA implementation and verification, which is time-consuming and sometimes incompatible with certain designs. To develop this new methodology, it is necessary to export a series of functions or tasks defined in SystemVerilog to Python. For this purpose, the DPI (Direct Programming Interface) between SystemVerilog and the C language has been used, which allows calling C functions from SystemVerilog and exporting others from SystemVerilog to be called from C. Subsequently, using the SWIG (Simplified Wrapper and Interface Generator) tool, a Python test bench will be generated that will allow access to the functions generated in C that communicate with the UVM test bench or with the physical test bench.

[EN] In the world of algorithm acceleration and the implementation of deep neural networks' recall phase, OpenCL based solutions have a clear tendency to produce perfectly adapted kernels in graphic processor unit (GPU) architectures. However, they fail to obtain the same results when applied to field-programmable gate array (FPGA) based architectures. This situation, along with an enormous advance in new GPU architectures, makes it unfeasible to defend an acceleration solution based on FPGA, even in terms of energy efficiency. Our goal in this paper is to demonstrate that multikernel structures can be written based on classic systolic arrays in OpenCL, trying to extract the most advanced features of FPGAs without having to resort to traditional FPGA development using lower level hardware description languages (HDLs) such as Verilog or VHDL. This OpenCL methodology is based on the intensive use of channels (IntelFPGA extension of OpenCL) for the communication of both data and control and on the refinement of the OpenCL libraries using register transfer logic (RTL) code to improve the performance of the implementation of the base and activation functions of the neurons and, above all, to reflect the importance of adequate communication between the layers when implementing neuronal networks

[ES] El objetivo de este Trabajo Fin de Máster es desarrollar una Verification IP (VIP). Una VIP es una IP desarrollada utilizando lenguajes de descripción hardware (HDL) que tiene como finalidad garantizar el correcto funcionamiento de otro módulo hardware. Una VIP estudia el comportamiento del módulo, así como sus entradas y salidas, además de analizar el tratamiento de la información que se lleva a cabo en dicho módulo. Los resultados obtenidos en este proceso se contrastan con un modelo de referencia o modelo Golden, que se utiliza como ejemplo de funcionamiento correcto y como objetivo en la verificación del módulo en cuestión o DUT (Device Under Test). El desarrollo se realizará en un entorno UVM (Universal Verification Methodology), una metodología de verificación de vanguardia que posee ciertas ventajas respecto a metodologías tradicionales de verificación. El protocolo que verificará esta VIP desarrollada como parte del TFM es el PCIe o PCI express (Peripheral Component Interconnect express). Dicho protocolo tiene una gran relevancia en el mercado de las telecomunicaciones y de la electrónica en general, ya que se utiliza tanto en aplicaciones específicas de gran complejidad para la implementación de dispositivos en sistemas de mayor magnitud como en aplicaciones más simples destinadas a la denominada "electrónica de consumo". Maxlinear desarrolla circuitos integrados que hacen uso de dicho estándar, es por esa razón que está interesada en el desarrollo de una VIP que permita mejorar las tareas de validación de dichos dispositivos. La última generación de este estándar publicada es la quinta generación (PCIe Gen5), cuyas características son las que evaluará y verificará la VIP a desarrollar. Por tanto, en el presente TFM se desarrollará una VIP plenamente funcional que verifique un subset de las características del estándar PCIe y será diseñado con una arquitectura que permita fácilmente añadirle nuevas características del estándar en un futuro según las ne, [EN] The main goal of this Final Masters Project is to develop a Verification IP (VIP). A VIP is an IP that is developed using hardware description languages (HDL) and that aims to guarantee that the performance of another hardware module is correct. A VIP studies the behaviour of the module, as well as its inputs and outputs, analysing also how information is managed inside the module. The results obtained from this analysis are compared with the ones obtained from a reference (or Golden) model, used in the verification as an example of the correct behaviour that is expected to be achieved in the DUT (Device Under Test). The whole development will be done in a UVM (Universal Verification Methodology) environment, a cutting edge verification methodology that provides significant improvements regarding the conventional hardware verification flow. The protocol for which this VIP is developed as Final Masters Project is PCIe, also known as PCI Express (Peripheral Component Interconnect express). This protocol is hugely relevant in the current telecommunications and electronics market, as it is used for both specific complex applications that are meant to be implemented in greater systems, and simpler applications for consumer electronics. Maxlinear is a company that develops integrated circuits that use this standard bus, which is the reason why they are interested in the development of a VIP that could improve the verification tasks related to these ICs. The latest release of this PCIe standard is the fifth generation (PCIe Gen5) and those features in the standard are the ones that are going to be verified by the VIP. Thus, the developed PCIe VIP (as Final Masters Project) will check a subset of the features in the PCIe standard, and will be designed prioritising scalability, in order to make it suitable to add new features and related checkers from PCIe specification in the near future, according to the needs of the company. The verification of the VIP itself will be

[EN] The European Higher Education Area (EHEA) defines the competences for professional practice of a Telecommunications Engineer. The School of Telecommunication Engineering of the Universitat Politècnica de València (Valencia, Spain) provides an integrated education program consisting of a Graduate (GITST) + Master (MUIT). The GITST course offers four specialization tracks: Electronics, Telematics, Communication Systems and Multimedia for the proper acquisition of knowledge and competences of the future Telecommunications Engineers. In 2018, the graduate program has implemented a structural change in the organization of subjects for reinforcing important skills, in which a course on digital electronics design and verification (Integration of Digital Systems, ISDIGI) has been transformed into a core subject of the study plan. In this paper, we describe the methodology and adaptation of ISDIGI (i.e. a project-based learning intermediate HDL course that includes design and verification abilities) to the new GITST Curriculum. In addition, this paper describes the process of moving from specialized to core subject.

[ES] El objetivo de esta investigación es el estudio y evaluación de la aplicación del catalizador gastado de craqueo catalítico (FCC) como posible material de intervención en edificios patrimoniales de tierra. Cuando esta arquitectura es sometida a un proceso de intervención se debe priorizar la estabilización material y recuperación de las propiedades originales, tratando de buscar la máxima efectividad, durabilidad e integración de la intervención planteada. El proceso de consolidación y reposición del material dañado, permiten la devolución de las propiedades y configuración pérdidas, considerándose por ello como tratamientos clave en intervenciones sobre el patrimonio actual. Con el fin de ampliar mejoras y nuevos métodos sobre este proceso, la investigación sobre materiales aplicados y de nuevo desarrollo se cree fundamental. El estudio realizado trata de probar y evaluar las características de tres posibles materiales de intervención, los cuales presentan adición de FCC, y determinar su viabilidad en las metodologías de intervención más comunes. En la actualidad este producto procedente de la industria petroquímica, tiene la consideración de residuo inerte él cual carece de utilidad, por lo que desde hace unos años se ha profundizado en su estudio. Esta investigación ha tomado como base el estudio realizado por Piles et al. (2005), donde se destaca la posibilidad de emplear el FCC en morteros de restauración. Al partir de esta conclusión, el estudio que se presenta se centrará en concretar las propiedades aportadas por el FCC en dichos materiales y concluir en las posibilidades de empleo de este en intervenciones., [EN] The overall aim of this research is the study an evaluation of the application of the Fluid Catalityc Cracking (FCC) as a possible consolidating soil in heritage buildings. When this architecture is subjected to an intervention process, the stabilization of the damaged material must be prioritized, with the aim of producing greater durability and integration with the proposed intervention. The consolidation process is undertaken so as to return the building to its original state, which is deemed to be a key process in interventions in current heritage. In order to broaden improvements and new methods regarding this process, the research upon applied materials and new developments are believed to be fundamental. The goal of the carried out study is so as to determine the structural properties which confirm FCC as being a possible consolidating material, evaluating a range of its applications, whilst testing its viability during these processes. This product is currently considered to be inert waste coming from the petrochemical industry, which serves no purpose, therefore research in this field has deepend in recent years. This investigation is in part based on the study carried out by Piles et al. (2005), which confirms the possibility of applying the FCC in mortar restoration. Based on this conclusion, the research presented will focus on specifying the properties contributed and the alterations that its use can entail, with the aim of allowing a greater characterization.

[ES] El trabajo que se plantea consiste en el desarrollo de un entorno virtual para realización de entrenamiento motor para rehabilitación motora basado en el sistema de realidad virtual Oculus Rift combinado con el sistema Microsoft Kinect. El entorno se modelará haciendo uso de una herramienta de modelado 3D y se programará haciendo uso de la aplicación Unity. El sistema deberá realizar un seguimiento (tracking) preciso de la posición instantánea del cuerpo del usuario. Deberá incluir un avatar para representar al usuario, el cual se moverá en base a los movimientos reales realizados por el mismo y detectados con la Kinect. La aplicación deberá permitir al usuario final realizar distintos tipos de ejercicios e incluir medidas de la precisión del usuario en la realización de los mismos., [EN] The present project consists in the development of a motor training virtual environment for motor rehabilitation based on the Oculus Rift virtual reality system combined with the Microsoft Kinect system. The environment will be modelled using a 3D modelling tool and will be programmed with Unity. The system should track with precision the instantaneous position of the user body. It should include an avatar to represent the user, which will move according to the real movements performed by the user and detected by the Kinect. The application should allow different kinds of exercises and include measures of the precision of the user when performing the tasks.

[ES] A partir de la prueba de concepto realizada en un TFG anterior sobre el uso de la Realidad Aumentada para la visita al Mueso de la Telecomunicación, se pretende desarrollar una aplicación plenamente funcional que resuelva tanto los problemas técnicos como la usabilidad, y que permita añadir contenidos en diferentes formatos: animaciones, vídeos, audios, textos,, etc. Además la aplicación se completará con información estática sobre el Museo. El desarrollo de la aplicación será sobre Unity y Vuforia para diferentes plataformas.

[ES] En la evaluación de distintos chips es necesario generar patrones en sus señales de entrada y comprobar que las de salida sean correctas. Estos patrones deben cubrir todas las posibilidades del chip para asegurar su correcto funcionamiento en cualquier situación y modo de trabajo. El objetivo de este TFM es implementar un generador de patrones utilizando una FPGA que también sea capaz de capturar las salidas del chip. El uso de la FPGA permite tener un control total sobre qué señales se envían y reciben a través de sus pines, dónde se sitúan los flancos y, además, permite trabajar a una frecuencia superior a varias soluciones actuales. En este proyecto, los patrones serán generados a nivel de bit mediante scripts en Python en un PC y se cargarán a la FPGA a través de un puerto USB. La tarea de la FPGA será enviar estos patrones y recibir las señales del chip a evaluar., [EN] In the evaluation of different chips it is necessary to generate patterns in their input signals and check that the output signals are correct. These patterns must cover all the possibilities of the chip to ensure its correct performance in any situation and working mode. The objective of this TFM is to implement a pattern generator using an FPGA that is also capable of capturing the outputs of the chip. The use of the FPGA allows total control over which signals are sent and received through their pins, where the edges are located and, in addition, allows to work at a higher frequency than several current solutions. In this project, the patterns will be generated at bit level using Python scripts on a PC and will be uploaded to the FPGA through a USB port. The task of the FPGA will be to send these patterns and receive signals from the chip to be evaluated.

[ES] El objetivo fundamental del presente trabajo es desarrollar un core IP de procesador RISC-V en SystemVerilog que soporte de manera completa el ISA (Instruction Set Architecture) RV32IM, tanto en su versión Single Cycle, como en su versión Multi Cycle. La aplicación del core está orientada a la implementación de un SoC (System-on-Chip) en dispositivos programables de bajo coste y consumo de potencia, por lo que su concepción está orientada a la minimización de los recursos necesarios para su implementación. Además, se detallan los pasos a seguir para instalar y configurar una toolchain para arquitecturas de 32 bits que permita la ejecución de software compilado en C sobre el procesador diseñado, así como el desarrollo de una aplicación con interfaz gráfica que permita realizar la compilación del software y cargar los archivos generados de forma sencilla en el procesador. También se muestran los testbenches que se han ejecutado sobre el procesador para comprobar su correcto funcionamiento y comparar el rendimiento de las versiones Single Cycle y Multi Cycle., [EN] The main objective of this project is to develop a RISC-V processor IP core in SystemVerilog that fully supports the RV32IM ISA (Instruction Set Architecture), both in its Single Cycle version and in the Multi Cycle version. The application of the core is oriented to the implementation of a SoC (System-on-Chip) in programmable devices of low cost and power consumption. Thus, its conception is oriented to the minimization of the necessary resources for its implementation. In addition, the steps to be followed to install and configure a toolchain for 32-bit architectures that allow the execution of software compiled in C on the designed processor are detailed, as well as the development of an application with a graphic interface that allows compiling the software and load the generated files in a simple way in the processor. The testbenches that have been executed on the processor are also shown to check its correct operation and compare the performance of the Single Cycle and Multi Cycle versions.

[ES] El Doppler Transcraneal (TCD) es una técnica de diagnóstico por ultrasonidos de gran resolución temporal que monitoriza las características hemodinámicas de las arterias cerebrales principales. Para el análisis de las señales registradas, suelen aplicarse técnicas de tratamiento de señal muy básicas, basadas principalmente en la obtención de parámetros estadísticos. Sin embargo, para poder caracterizar la señal, es necesario realizar un análisis que combine distintas técnicas de procesado basadas en el análisis temporal, espectral, tiempo-frecuencia o la teoría de la información. El trabajo que se plantea consiste en la programación en Matlab de métodos más avanzados de análisis que permitan extraer características relevantes de la señal de TCD. Los algoritmos de preprocesado y de obtención de características se programarán de forma genérica para permitir su aplicación en distintos tipos de estudios. Se realizará una validación del funcionamiento de los mismos con datos ya disponibles de un estudio en el que se ha registrado la velocidad de flujo sanguíneo en las arterias cerebrales anteriores y medias utilizando TCD.

Implicado en el desarrollo de cualquier circuito integrado encontramos al ingeniero de evaluación de diseño. Esta persona es responsable de la verificación física del comportamiento de un chip después de su diseño. Cualquier problema o defecto de diseño será reportado por este ingeniero y corregido en nuevas revisiones del circuito integrado. La forma en que este ingeniero determina si un chip o una funcionalidad cumple las especificaciones es mediante la realización de pruebas en un laboratorio de evaluación. En este lugar, encontramos todos los instrumentos necesarios para realizar las pruebas, como multímetros de precisión, osciloscopios, fuentes de alimentación, generadores de formas de onda, sistemas de forzado de temperatura y tarjetas programables de comunicación. Una vez corregidos todos los problemas, el circuito integrado puede seguir adelante e iniciar la etapa de producción, caracterización en masa y comercialización. El objetivo de este Proyecto de Fin del Grado en Ingeniería de Tecnologías y Servicios de Telecomunicación es mostrar la contribución a la caracterización del chip mediante la explicación de las pruebas realizadas y la exposición de los resultados obtenidos., Implied in the development of any integrated circuit we find the design evaluation engineer. This person is responsible for the physical verification of the behavior of a chip after its design. Any issue or design flaw shall be reported by this engineer and corrected in new revisions of the integrated circuit. The way this engineer determines whether if a chip or a functionality complies specs is by running tests on an evaluation laboratory. In such place, we find all the needed instruments to run the tests, like precision multimeters, oscilloscopes, power supplies, waveform generators, forced- temperature systems and programmable communication cards. After all the issues are corrected, the integrated circuit can go forward and start the production, mass characterization and market stage. The aim of this Final Project for the bachelor s degree in Telecommunications Engineering is to show the contribution to the characterization of the chip by explaining the tests made to it and exposing the results obtained.

[EN] In this contribution, large SiPM arrays (8 x 8 elements of 6 x 6 mm(2) each) are processed with an ASIC-based readout and coupled to a monolithic LYSO crystal to explore their potential use for TOF-PET applications. The aim of this work is to study the integration of this technology in the development of clinical PET systems reaching sub-300 ps coincidence resolving time (CRT). The SiPM and readout electronics have been evaluated first, using a small size 1.6 mm (6 mm height) crystal array (32 x 32 elements). All pixels were well resolved and they exhibited an energy resolution of about 20% (using Time-over-Threshold methods) for the 511 keV photons. Several parameters have been scanned to achieve the optimum readout system performance, obtaining a CRT as good as 330 +/- 5 ps FWHM. When using a black-painted monolithic block, the spatial resolution was measured to be on average 2.6 +/- 0.5 mm, without correcting for the source size. Energy resolution appears to be slightly above 20%. CRT measurements with the monolithic crystal detector were also carried out. Preliminary results as well as calibration methods specifically designed to improve timing performance, are being analyzed in the present manuscript.

[EN] Neurofeedback is a self-regulation technique that can be applied to learn to voluntarily control cerebral activity in specific brain regions. In this work, a Transcranial Doppler-based configurable neurofeedback system is proposed and described. The hardware configuration is based on the Red Pitaya board, which gives great flexibility and processing power to the system. The parameter to be trained can be selected between several temporal, spectral, or complexity features from the cerebral blood flow velocity signal in different vessels. As previous studies have found alterations in these parameters in chronic pain patients, the system could be applied to help them to voluntarily control these parameters. Two protocols based on different temporal lengths of the training periods have been proposed and tested with six healthy subjects that were randomly assigned to one of the protocols at the beginning of the procedure. For the purposes of the testing, the trained parameter was the mean cerebral blood flow velocity in the aggregated data from the two anterior cerebral arteries. Results show that, using the proposed neurofeedback system, the two groups of healthy volunteers can learn to self-regulate a parameter from their brain activity in a reduced number of training sessions.

1.- Se trata de caracterizar la distorsión que generan los transistores que componen un amplificador operacional. En particular, de todos los amplificadores que contiene un AFE (Analog-Front-End) nos fijaremos en el driver de salida, ya que es éste el que genera mayor distorsión. Se trata de obtener una simulación en tiempo real de estos valores, y de esta forma, poder corregirla en la parte digital del circuito integrado. Tener un modelo de distorsión implica ventajas tanto para el cliente, reflejadas en unas especificaciones mucho más precisas del AFE como para el departamento de diseño digital, el cual es el encargado de hacer la corrección de dicha distorsión. El objetivo es conocer cuál es el valor MTPR que podemos manejar en cada etapa del AFE, especialmente el valor inicial y tendencia. 2.- El objetivo es realizar el firmware de test mediante comandos AT. Este firmware tiene que comprobar el correcto funcionamiento de todos los ADC, DAC y memoria FLASH que componen el diseño de la FPGA. Para que la verificación se realice en cualquier laboratorio sin necesidad de conocimientos de diseño hardware, se ha diseñado el test mediante comandos AT. Se combina la parte de control mediante software (microblaze) y la parte hardware mediante los diferentes módulos programados en VHDL. La comunicación de los periféricos se realiza a través del bus PLB, ya que se trata de una Spartan3. Se ha programado una librería tanto para la comunicación de los registros de los ADC y DAC como la comunicación mediante SPI de la memoria FLASH. Dentro de la FPGA se dispone de tres dominios de reloj por lo que es necesario el uso de registros para evitar posibles casos de metaestabilidad.

El desarrollo de este TFM se basa en la necesidad de realizar avances en los sistema de radio por software que existen. Estos sistemas son capaces de analizar las señales en un espectro muy amplio con diferentes tipos de anchos de banda. Cuando el ancho de banda de las señales es muy grande es necesario basarse en sistemas con FPGA. La recepción de los datos se realizará mediante un ADC de alta resolución y tasa de muestreo suficiente para el ancho de banda requerido. Los datos recibidos se procesarán y se realizará un sistema de transmisión para enviar los datos a un sistema externo. Habrá que realizar, la integración en la FPGA de las diferentes plataformas que componen el sistema: ADC, FPGA y microprocesador; así como el software de configuración del ADC, transmisión de datos y test de las diferentes partes.

[EN] Developing front-end electronics to improve charge detection and time resolution in gamma-ray detectors is one of the main tasks to improve performance in new multimodal imaging systems that merge information of Magnetic Resonance Imaging and Gamma Camera or PET tomographs. The aim of this work is to study the behaviour and to optimize the performance of an ASIC for PET and Gamma Camera applications based on SiPMs detectors. PETIROC2 is a commercial ASIC developed by Weeroc to provide accurate charge and time coincidence resolutions. It has 32 analog input channels that are independently managed. Each channel is divided into two signals, one for time stamping using a TDC and another for charge measurement. In this work, PETIROC2 is evaluated in an experimental setup composed of two pixelated LYSO crystals based detectors, each coupled to a Hamamatsu 4 x 4 SiPM array. Both detectors are working in coincidence with a separation distance between them that can be modified. In the present work, an energy resolution of 13 : 6% FWHM and a time coincidence resolution of 815 ps FWHM have been obtained. These results will be useful to optimize and improve PETIROC2 based PET and Gamma Camera systems.

A DAQ architecture for a PET system is presented that focuses on modularity, scalability and reusability. The system defines two basic building blocks: data acquisitors and concentra- tors, which can be replicated in order to build a complete DAQ of variable size. Acquisition modules contain a scintillating crystal and either a position-sensitive photomultiplier (PSPMT) or an array of silicon photomultipliers (SiPM). The detector signals are processed by AMIC, an integrated analog front-end that generates programmable analog outputs which contain the first few statistical moments of the light distribution in the scintillator. These signals are digitized at 156.25 Msamples/s with free-run- ning ADCs and sent to an FPGA which detects single gamma events, extracts position and time information online using digital algorithms, and submits these data to a concentrator module. Concentrator modules collect single events from acquisition modules and perform coincidence detection and data aggregation. A synchronization scheme over data links is implemented that calibrates each link s latency independently, ensuring that there are no limitations on module mobility, and that the architecture is arbitrarily scalable. Prototype boards with both acquisition and concentration functionality have been built for evaluation pur- poses. The performance of a small PET system with two detectors based on continuous scintillators is presented. A synchronization error below 50 ps rms is measured, and energy resolutions of 19% and 24% and timing resolutions of 2.0 ns and 4.7 ns FWHM are obtained for PMT and SiPM photodetectors, respectively.

[EN] In this work we describe a procedure to reduce the number of signals detected by an array of 256 Silicon Photo-multipliers (SiPMs) using a resistor network to divide the signal charge into few readout channels. Several configurations were modeled, and the pulsed signal at the readout contacts were simulated. These simulation results were experimentally tested on a specifically designed and manufactured set of printed circuit boards. Three network configurations were modeled. The modeling provided encouraging results for all three configurations. The measurements on the prototypes constructed for this study, however, provided useful position-sensitivity for only one of the network configurations. The lack of input signal amplification into the networks, the SiPM dark current, as well as the complexity of an eight layers board with parasitic capacitances, could have caused the degradation of resolving the impact photon position. This is hard to overcome with external printed circuit boards and components.

[EN] Improving timing resolution in positron emission tomography (PET), thus having fine time information of the detected pulses, is important to increase the reconstructed images signal to noise ratio (SNR) [1]. In the present work, an integrated circuit topology for time extraction of the incoming pulses is evaluated. An accurate simulation including the detector physics and the electronics with different configurations has been developed. The selected architecture is intended for a PET system based on a continuous scintillation crystal attached to a SiPM array. The integrated circuit extracts the time stamp from the first few photons generated when the gamma-ray interacts with the scintillator, thus obtaining the best time resolution. To get the time stamp from the detected pulses, a time to digital converter (TDC) array based architecture has been proposed as in [2] or [3]. The TDC input stage uses a current comparator to transform the analog signal into a digital signal. Individually configurable trigger levels allow us to avoid false triggers due to signal noise. Using a TDC per SiPM configuration results in a very area consuming integrated circuit. One solution to this problem is to join several SiPM outputs to one TDC. This reduces the number of TDCs but, on the other hand, the first photons will be more difficult to be detected. For this reason, it is important to simulate how the time resolution is degraded when the number of TDCs is reduced. Following this criteria, the best configuration will be selected considering the trade-off between achievable time resolution and the cost per chip. A simulation is presented that uses Geant4 for simulation of the physics process and, for the electronic blocks, spice and Matlab. The Geant4 stage simulates the gamma-ray interaction with the scintillator, the photon shower generation and the first stages of the SiPM. The electronics simulation includes an electrical model of the SiPMarray and all the integrated circuitr

NOTICE: this is the author’s version of a work that was accepted for publication in Nuclear Instruments and Methods in Physics Research Section A. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Nuclear Instruments and Methods in Physics Research Section A, Volume 702, 21 February 2013, Pages 94–97 DOI 10.1016/j.nima.2012.08.028, In this paper we describe the overall design of a PET–MR system for head imaging within the framework of the DREAM Project as well as the first detector module tests. The PET system design consists of 4 rings of 16 detector modules each and it is expected to be integrated in a head dedicated radio frequency coil of an MR scanner. The PET modules are based on monolithic LYSO crystals coupled by means of optical devices to an array of 256 Silicon Photomultipliers. These types of crystals allow to preserve the scintillation light distribution and, thus, to recover the exact photon impact position with the proper characterization of such a distribution. Every module contains 4 Application Specific Integrated Circuits (ASICs) which return detailed information of several light statistical momenta. The preliminary tests carried out on this design and controlled by means of ASICs have shown promising results towards the suitability of hybrid PET–MR systems.

[EN] Silicon photomultipliers (SiPM) are the photon detectors chosen for the tracking readout in NEXT, a neutrinoless \bb decay experiment which uses a high pressure gaseous xenon time projection chamber (TPC). The reconstruction of event track and topology in this gaseous detector is a key handle for background rejection. Among the commercially available sensors that can be used for tracking, SiPMs offer important advantages, mainly high gain, ruggedness, cost-effectiveness and radio-purity. Their main drawback, however, is their non sensitivity in the emission spectrum of the xenon scintillation (peak at 175 nm). This is overcome by coating these sensors with the organic wavelength shifter tetraphenyl butadiene (TPB). In this paper we describe the protocol developed for coating the SiPMs with TPB and the measurements performed for characterizing the coatings as well as the performance of the coated sensors in the UV-VUV range. © 2012 IOP Publishing Ltd and SISSA.

[EN] AMIC architecture has been introduced in previous works in order to provide a generic and expandable solution for implementing large number of outputs SiPM array/PMT detectors. The underlying idea in AMIC architecture is to calculate the moments of the detected light distribution in an analog fashion. These moments provide information about energy, x/y position, etc. of the light distribution of the detected event. Moreover this means that a small set of signals contains most of the information of the event, thus reducing the number of channels to be acquired. This paper introduces a new front-end device AMIC2GR which implements the AMIC architecture improving the features of the former integrated devices. Higher bandwidth and filtering coefficient precision along with a lower noise allow to apply some detector enhancements. Inhomogeneity among detector elements throughout the array can be reduced. Depth of interaction measurements can be obtained from the light distribution analysis. Also a common trigger signal can be obtained for the whole detector array. Finally AMIC2GR preamplifier stage close to SiPM output signals optimizes signal to noise ratio, which allows to reduce SiPM gain by using lower operating voltages thus reducing dark noise

NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-ß decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz. © 2011 Elsevier B.V.

NEXT is a new experiment to search for neutrinoless double beta decay using a 100 kg radio-pure high-pressure gaseous xenon TPC with electroluminescence readout. A large-scale prototype with a SiPM tracking plane has been built. The primary electron paths can be reconstructed from time-resolved measurements of the light that arrives to the SiPM plane. Our approach is to measure how many photons have reached each SiPM sensor each microsecond with a gated integrator. We have designed and tested a 16-channel front-end board that includes the analog paths and a digital section. Each analog path consists of three different stages: a transimpedance amplifier, a gated integrator and an offset and gain control stage. Measurements show good linearity and the ability to detect single photoelectrons. © 2011 Elsevier B.V.

[EN] In this Technical Design Report (TDR) we describe the NEXT-100 detector that will search for neutrinoless double beta decay (ßß0v) in 136XE at the Laboratorio Subterráneo de Canfranc (LSC), in Spain. The document formalizes the design presented in our Conceptual Design Report (CDR): an electroluminescence time projection chamber, with separate readout planes for calorimetry and tracking, located, respectively, behind cathode and anode. The detector is designed to hold a maximum of about 150 kg of xenon at 15 bar, or 100 kg at 10 bar. This option builds in the capability to increase the total isotope mass by 50% while keeping the operating pressure at a manageable level. The readout plane performing the energy measurement is composed of Hamamatsu R11410-10 photomultipliers, specially designed for operation in low-background, xenon-based detectors. Each individual PMT will be isolated from the gas by an individual, pressure resistant enclosure and will be coupled to the sensitive volume through a sapphire window. The tracking plane consists in an array of Hamamatsu S10362-11-050P MPPCs used as tracking pixels. They will be arranged in square boards holding 64 sensors (8 x 8) with a 1-cm pitch. The inner walls of the TPC, the sapphire windows and the boards holding the MPPCs will be coated with tetraphenyl butadiene (TPB), a wavelength shifter, to improve the light collection. © 2012 IOP Publishing Ltd and Sissa Medialab srl.

La Tomografía por emisión de positrones (PET, Positron Emission Tomography) es una técnica de diagnóstico médico que se encarga de mostrar imágenes de la distribución de radioisótopos dentro del cuerpo, permitiendo de esta forma observar procesos metabólicos que ocurren en su interior. Los sistemas PET se encargan de detectar pares de rayos gamma de 511KeV cada uno generados tras la aniquilación de un positrón con un electrón. De cada rayo gamma detectado, obtenemos su energía, la posición en la que el rayo es detectado y el tiempo exacto en el que el evento ha sido detectado. Denominamos tiempo de coincidencia a la diferencia de tiempos entre dos eventos. La resolución temporal de un sistema vendrá determinada por el error temporal cometido en la medida del tiempo de coincidencia. Una mejora en la resolución temporal implica una reducción del ruido de las imágenes generadas en el sistema PET. Tradicionalmente, las técnicas para la extracción del tiempo de un evento recibido han sido implementadas analógicamente. Estas técnicas permiten alcanzar una resolución temporal muy elevada. Sin embargo, la electrónica usada en las técnicas analógicas está muy adaptada a un detector específico, es compleja y poco configurable. La búsqueda de coincidencias en sistemas con muchos detectores que hacen uso de técnicas analógicas se vuelve un gran problema, pues hace necesario un incremento de la complejidad de la electrónica muchas veces inabordable. Existe una tendencia actual a reducir la electrónica analógica de los sistemas PET sustituyéndola por electrónica digital mediante una temprana digitalización de las señales de los detectores. Por tanto, deben proponerse y estudiarse algoritmos digitales para la extracción de una marca temporal de los eventos detectados. Por el momento, las técnicas digitales actuales no alcanzan las resoluciones temporales de las técnicas analógicas. El presente estudio se enmarca dentro del ámbito de los discriminadores de tiempo digitales. En el g

Current PET systems with fully digital trigger rely on early digitization of detector signals and the use of digital processors, usually FPGAs, for recognition of valid gamma events on single detectors. Timestamps are assigned and later used for coincidence analysis. In order to maintain a decent timing resolution for events detected on different acquisition boards, it is necessary that local timestamps on different FPGAs be synchronized. Sub-nanosecond accuracy is mandatory if we want this effect to be negligible on overall timing resolution. This is usually achieved by connecting all boards to a common backplane with a precise clock delivery network; however, this approach forces a rigid structure on the whole PET system and may pose scalability problems. © 2006 IEEE.

Conventional readout systems exist in many variants since the usual approach is to build readout electronics for one given type of detector. The Scalable Readout System (SRS) developed within the RD51 collaboration relaxes this situation considerably by providing a choice of frontends which are connected over a customizable interface to a common SRS DAQ architecture. This allows sharing development and production costs among a large base of users as well as support from a wide base of developers. The Front-end Concentrator card (FEC), a RD51 common project between CERN and the NEXT Collaboration, is a reconfigurable interface between the SRS online system and a wide range of frontends. This is accomplished by using application-specific adapter cards between the FEC and the frontends. The ensemble (FEC and adapter card are edge mounted) forms a 6U x 220mm Eurocard combo that fits on a 19 '' subchassis. Adapter cards exist already for the first applications and more are in development.

Coincidence time resolution is one of the most important issues in PET detectors. Improving this resolution is required to increase the noise equivalent count rate (NECR) that reduces the noise in the reconstructed images. The aim of this work is to evaluate the behavior and time resolution of different proposed time pick-off algorithms in order to select the best configuration for our PET system. The experimental setup used for this research is composed by two monolithic LSO crystals+ PSPMT detectors and an FPGA based PET data acquisition system (DAQ). The acquired signals are sampled using a 12-bit 70 MHz analog to digital converter (ADC) per channel. The setup has no centralized electronics for trigger and event time extraction. Consequently, events for each detector head are processed independently and all the signals are acquired in the same way. Time resolution in this kind of systems can be improved by means of digital processing techniques and using different shapings for the last dynode signals. Four digital algorithms extracting time information from the acquired pulses have been evaluated: (1) Amplitude bipolar digital constant fraction discriminator (BCFD), (2) charge BCFD, (3) interpolated amplitude BCFD and (4) interpolated charge BCFD. Two different architectures for the interpolation algorithm have been used (one-sample and two-sample interpolation), which allow us to work with two different FPGA internal sampling frequencies: 140 MHz and 210 MHz. The results show the importance of selecting the right algorithm and parameters. Time coincidence resolution in our hardware system can be improved by up to 6.9 ns FWHM depending on the chosen digital algorithm programmed on the FPGA. The measurements with our setup reveal that charge based algorithms are less sensitive to signal noise and generate better results than amplitude algorithms. The best configuration achieves a FWHM resolution close to 1.8 ns. © 2006 IEEE.

In this article we introduce AMIC (Analog Moments Integrated Circuit), a novel analog Application Specific Integrated Circuit (ASIC) front-end for Positron Emission Tomography (PET) applications. Its working principle is based on mathematical analysis of light distribution through moments calculation. Each moment provides useful information about light distribution, such as energy, position, depth of interaction, skewness (deformation due to border effect) etc. A current buffer delivers a copy of each input current to several processing blocks. The current preamplifier is designed in order to achieve unconditional stability under high input capacitance, thus allowing the use of both Photo-Multiplier Tubes (PMT) and Silicon Photo-Multipliers (SiPM). Each processing block implements an analog current filtering by multiplying each input current by a programmable 8-bit coefficient. The latter is implemented through a high linear MOS current divider ladder, whose high sensitivity to variations in output voltages requires the integration of an extremely stable fully differential current collector. Output currents are then summed and sent to the output stage, that provides both a buffered output current and a linear rail-to-rail voltage for further digitalization. Since computation is purely additive, the 64 input channels of AMIC do not represent a limitation in the number of the detector's outputs. Current outputs of various AMIC structures can be combined as inputs of a final AMIC, thus providing a fully expandable structure. In this version of AMIC, 8 programmable blocks for moments calculation are integrated, as well as an I2C interface in order to program every coefficient. Extracted layout simulation results demonstrate that the information provided by moment calculation in AMIC helps to improve tridimensional positioning of the detected event. A two-detector test-bench is now being used for AMIC prototype characterization and preliminary results are presented. © 20

Conventional readout systems exist in many variants since the usual approach is to build readout electronics for one given type of detector. The Scalable Readout System (SRS) developed within the RD51 collaboration relaxes this situation considerably by providing a choice of frontends which are connected over a customizable interface to a common SRS DAQ architecture. This allows sharing development and production costs among a large base of users as well as support from a wide base of developers. The Front-end Concentrator card (FEC), a RD51 common project between CERN and the NEXT Collaboration, is a reconfigurable interface between the SRS online system and a wide range of frontends. This is accomplished by using application-specific adapter cards between the FEC and the frontends. The ensemble (FEC and adapter card are edge mounted) forms a 6U × 220 mm Eurocard combo that fits on a 19'' subchassis. Adapter cards exist already for the first applications and more are in development. © 2011 IOP Publishing Ltd and SISSA.