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Review and Proposed Model” [Al-Janahi, N. et al, 2019] in which we proposed a model for adoption of biometrics in online banking system in Kuwait. The research started by developing a model for measuring the customers’ acceptance of biometrics adoption in online banking in Kuwait. Self-administered questionnaires were distributed through SurveyMonkey.com platform. A total of 500 invitations were sent and 302 valid responses were received. The data was analysed using SPSS software tool, version 22. Analyses such as descriptive, correlation, regression, t-test and one-way ANOVA were conducted on the collected data to test their relationships and significance. The results revealed that self-efficacy, perceived behavioural control, reliability, appearance, support, content, safety and privacy are important parameters that need to be carefully addressed by the bank management while considering adoption of Biometrics in online banking in Kuwait. Bank management need also to ensure that the intended biometric system is easy to use, that it provides the expected usefulness, and that it ensures high level of convenience and that it earns (secures) customers’ trust and satisfaction.

Ant Colony Optimization and Particle Swarm Optimization represent two widely used Swarm Intelligence (SI) optimization techniques. Information processing using Multiple-Valued Logic (MVL) is carried out using more than two discrete logic levels. In this paper, we compare two the SI-based algorithms in synthesizing MVL functions. A benchmark consisting of 50,000 randomly generated 2-variable 4-valued functions is used for assessing the performance of the algorithms using the benchmark. Simulation results show that the PSO outperforms the ACO technique in terms of the average number of product terms (PTs) needed. We also compare the results obtained using both ACO-MVL and PSO-MVL with those obtained using Espresso-MV logic minimizer. It is shown that on average, both of the SI-based techniques produced better results compared to those produced by Espresso-MV. We show that the SI-based techniques outperform the conventional direct-cover (DC) techniques in terms of the average number of product terms required.

The speed and area performance of the byte-substitution (S-Box) impose a correlated impact on the speed and area of the Advanced Encryption System (AES) cryptosystem. In this paper, we present an efficient realization technique of the S-Box in the AES cryptosystem. We start by classifying the S-Box byte-substitution design techniques. We then provide a brief coverage of the hardware, software, and hybrid S-Box realization techniques. We then present an efficient S-Box realization technique that replaces the search needed in the 16 ×16 S-Box by four simpler searches two of them can be conducted in parallel and in a way that reduces the final search into searching within a set consisting of only four 2×2 cells which in turn leads to a faster search strategy. We also provide a simple hardware to carry out the search. A performance comparison among five realization techniques is conducted. The comparison is based in terms of the area (A) and the delay (T). It is shown that the technique due to Bertoni is the fastest followed by the technique due to Abd-El-Barr. In terms of area, it was found out that the technique due to Abd-El-Barr consumes the least area followed by the technique due to Canright. The technique due to Abd-El-Barr achieves the best normalized O(AT2) where A is the area and T is the critical path delay.

The use of social media in Kuwait has clearly grown in a noticeable way. This growth has affected Kuwaitis in a number of ways. One such effect is in the political arena. This study investigates one aspect of the relationship between social media and politics in Kuwait. The plan is to study the impact of social media on politics in Kuwait from citizens' perspective. In particular, the study focuses mainly on the level of engagement of Kuwaitis citizens' in political issues. For instance, we investigate the role of social media in Kuwaitis' awareness, their participation and political involvement. Towards this objective, a survey has been conducted in February 2016 through which a sample of 637 Kuwaitis were surveyed about their use of social media in dealing with political issues. The collected data were analyzed using the statistical tool SPSS. Analysis of the obtained results reveals that Kuwaitis use social media platforms, especially Twitter, to help them express their political views as well as, accept others' political views. The results also showed that there exists a statistically significant relationship between using social media and the increased political awareness, political participation and attitude of Kuwaitis towards politics. In light of the results, a series of recommendations are made for Kuwaiti citizens, government officials and parliament members. Some suggestions for future studies are also provided.

Ant colony optimization (ACO) is a well-known optimization technique and has been extensively used to a solve a variety of computationally hard problems. One such hard problem is found in the domain of local area network (LAN) topological optimization. The problem, due to its various design objectives and technical constraints, is considered a complex optimization problem. Due to this complexity, use of an intelligent design algorithm is inevitable in order to obtain a quality solution in a reasonable time. This paper proposes a new intelligent optimization algorithm that integrates features of the ACO algorithm and the simulated evolution (SE) algorithm. The performance of the proposed hybrid algorithm, termed as ACOSE, is empirically evaluated and compared with the ACO and SE algorithms. Preliminary results indicate that ACOSE is able to produce better results on the LAN design problem considered herein in terms of quality of solution compared to either ACO or SE.

Due to the increase in design complexity and cost of VLSI chips, a number of design houses outsource manufacturing and import designs in a way to reduce the cost. This results in a decrease of the authenticity and security of the manufactured product. Since product development involves outside sources, circuit designers can not guarantee that their hardware has not been altered. It is often possible that attackers include additional hardware in order to gain privileges over the original circuit or cause damage to the product. These added circuits are called “Hardware Trojans”. In this paper, we investigate introducing necessary modules needed for detection of hardware Trojans. We also introduce necessary programmable logic fabric that can be used in the implementation of the hardware assertion checkers. Our target is to utilize the provided programable fabric in a System on Chip (SoC) and optimize the hardware assertion to cover the detection of most hardware trojans in each core of the target SoC.

A multi-computer system (MCS) offers the high speed and throughput needed in solving computing-intensive problems. Two main components constitute a MCS. These are the processing elements (PEs) and the interconnection network (IN). A faulty IN can lead to data losses and/or throughput degradation. Hence, it is necessary to consider the fault tolerance and reliability aspects in assessing the efficacy of INs. This paper provides coverage of the fault tolerance and reliability aspects of hypercube multi-computer networks (HCNs). In particular, we cover three broad aspects: task-based reliability, fault-tolerant routing, and communication in faulty HCNs. Our coverage includes introducing the particular HC architecture, analyze its reliability and assess its fault tolerance. The analysis provided in the paper is deemed helpful to HCN designers in making informed decisions about the appropriate approaches that can be used to assess the reliability and fault tolerance of existing HCNs.

Scheduling large-scale application in heterogeneous grid systems is a fundamental NP-complete problem that is critical to obtain good performance and execution cost. To achieve high performance in a grid system it requires effective task partitioning, resource management and load balancing. The heterogeneous and dynamic nature of a grid, as well as the diverse demands of applications running on the grid, makes grid scheduling a major task. Existing schedulers in wide-area heterogeneous systems require a large amount of information about the application and the grid environment to produce reasonable schedules. However, this required information may not be available, may be too expensive to collect, or may increase the runtime overhead of the scheduler such that the scheduler is rendered ineffective. We believe that no one scheduler is appropriate for all grid systems and applications. This is because while data parallel applications in which further data partitioning is possible can be further improved by efficient management of resources, smart selection of resources and load balancing can be possible, in functional/not-dividable-task parallel applications such partitioning is either not possible or difficult or expensive in term of performance. In this paper, we propose a scheduler for data parallel applications (SDPA) which offers an efficient task partitioning and load balancing strategy for data parallel applications in grid environment. The proposed SDPA offers two major features: maintaining job priority even if insufficient number of free resources is available and pre-task assignment to cut the idle time of nodes. The SDPA selects nodes smartly according to the nature of task and the nodes' resources availability. Simulation results conducted reveal that SDPA achieves performance improvement over reported strategies in the reviewed literature in terms of execution time, throughput and waiting time.

The performance of the S-Box represents an important factor in the overall performance of the AES cryptography systems. It affects the speed, area, and the power consumption of the AES. In attempts to improve the performance of the S-box byte substitution a number of techniques were presented in the literature. In this paper, we classify the S-box byte substitution optimization techniques as those based on hardware, software, and combined hardware/software. We then move on to propose a new highly parallel and area-efficient S-box architecture for AES byte substitution. We also conduct a performance analysis and comparison of the proposed architecture with those achieved by existing techniques. The comparison shows that the proposed architecture outperforms the existing techniques in terms of speed and area.

The Advanced Encryption Standard (AES) is the current world standard symmetric key block cipher cryptosystem for data encryption/decryption. Multi-valued logic (MVL) is a propositional calculus that goes beyond binary in terms of the number of truth values. There has been intensive research work conducted attempting to enhance the performance of cryptographic systems in terms of speed and area. We have previously presented the gate-level logic design of a number of Modulo-4 and Galois field (GF) arithmetic operations using both binary and MVL. In this paper, we follow up on our previous work by presenting the CMOS (Complementary Metal Oxide Semiconductor) design, implementation, and PSpice simulation of Modulo-4 and Galois field (GF) arithmetic operations using MVL. The design objective is to minimize the chip area (measured by the number of transistors in the CMOS circuit implementation). Also reported is the transient analysis using the 0.18µm CMOS technology parameters. A comparison is conducted between our proposed CMOS implementation and those reported in the literature. The chip area (measured in terms of number of transistors) required for our implementation is less than those needed by the existing implementations.

The use of non-binary (multiple-valued) logic in the synthesis of digital systems can lead to savings in chip area. Advances in very large scale integration (VLSI) technology have enabled the successful implementation of multiple-valued logic (MVL) circuits. A number of heuristic algorithms for the synthesis of (near) minimal sum-of products (two-level) realisation of MVL functions have been reported in the literature. The direct cover (DC) technique is one such algorithm. The ant colony optimisation (ACO) algorithm is a meta-heuristic that uses constructive greediness to explore a large solution space in finding (near) optimal solutions. The ACO algorithm mimics the ant's behaviour in the real world in using the shortest path to reach food sources. We have previously introduced an ACO-based heuristic for the synthesis of two-level MVL functions. In this article, we introduce the ACO–DC hybrid technique for the synthesis of multi-level MVL functions. The basic idea is to use an ant to decompose a given MV...

We consider the problem of topological optimization of communication networks subject to a number of design constraints, such as maximum network diameter, maximum node degree, k-node (link) survivability, and network fault tolerance. The primary design problem can be described as follows: Given a set of network nodes, it is required to find a topology @J, selected from all possible topologies, so that the cost of @J (measured possibly in terms of the maximum diameter, maximum node degree, etc.) is less than that of any other network topology and such that @J satisfies some given design constraints. Fault tolerance is concerned with the ability of the network nodes to communicate in the presence of a set of faulty links and/or nodes. The network design problem considering reliability constraints is NP-hard. We classify the research efforts presented in the literature for solving the topological optimization design problem as hierarchical, enumerative, or iterative techniques. In this paper, we provide a survey of the topological network design techniques under different design constraints. Experimental results obtained by applying a number of algorithms to a set of randomly generated networks are presented and compared.

Mobile computing systems provide users with access to information regardless of their geographical location. In these systems, Mobile Support Stations (MSSs) play the role of providing reliable and uninterrupted communication and computing facilities to mobile hosts. The failure of a MSS can cause interruption of services provided by the mobile system. Two basic schemes for tolerating the failure of MSSs exist in the literature. The first scheme is based on the principle of checkpointing used in distributed systems. The second scheme is based on state information replication of mobile hosts in a number of secondary support stations. Depending on the replication scheme used, the second approach is further classified as a pessimistic or an optimistic technique. In this paper, we propose a hybrid scheme which combines the pessimistic and the optimistic replication schemes. In the proposed scheme, an attempt is made to strike a balance between the long delay caused by the pessimistic and the high memory requirements of the optimistic schemes. In order to find the best ratio between the number of pessimistic to the number of optimistic secondary stations in the proposed scheme, we used fuzzy logic. We also used simulation to compare the performance of the proposed scheme with those of the optimistic and the pessimistic schemes. Simulation results showed that the proposed scheme performs better than either schemes in terms of delay and memory requirements.

The Advanced Encryption Standard (AES) is a symmetric key block cipher cryptosystem adopted by the NIST as the world standard for data encryption/decryption. Multi-valued logic (MVL), as opposed to two-valued logic (TVL), is a propositional calculus in which there are more than two truth values. Multiple-valued logic offers opportunities for overcoming a number of difficulties facing TVL such as chip area, power consumption, and delay. A number of researchers have conducted intensive research work in attempts to improve and enhance the performance of cryptographic systems in terms of speed, area, and power consumption. In this paper, we present a number of arithmetic operations required by the AES cryptosystem using both TVL and MVL. We also cover the Galois field arithmetic operations performed in cryptographic systems.

Statistical analysis of multiple intermittent faults (SAMIFs) is proposed as a method for estimating the detection probabilities and fault coverage of multiple intermittent faults in combinational circuits. SAMIFs involves the concurrent simulation of multiple intermittent faults and an estimation of the controllability and observability values for each node of the faulty circuit for a given set of input vectors. The controllabilities and observabilities are then used to derive estimates of the fault-detection probabilities and the overall fault coverage. An algorithm for estimating the fault coverage of a pseudo-random test vector set over a set of multiple intermittent faults in a combinational circuit is also proposed. Experimental results obtained from applying the algorithm to a number of benchmark circuits are also presented.

Testability should be considered as early as possible in VLSI synthesis and optimization. In most CAD tools, testability preservation is achieved as a by-product of finding a less redundant implementation. Unfortunately, this approach is not supported by theory. It is essential to have an optimization scheme that systematically preserves testability. A complete theory covering testability-preserving optimization of combinational circuits is yet to be developed.In this paper, a new testability-preserving theory is established. This theory covers most optimization cases in the synthesis of irredundant circuits. Optimization of redundant circuits is also considered. Algorithms based on this theory are proposed. Experiments to verify the theory and algorithms are reported. The developed theory and algorithms are more general than previous results.

In this brief, a divide-and-conquer based RNS (residue number system) decoding algorithm is proposed. The basic idea of this algorithm is to decompose a set of moduli into groups each of size two moduli and to decode a given number in a two moduli representation. The time complexity of the algorithm used is O(log n), where n is the size of the moduli set. There is no assumption made on the elements of the module set. In addition, the algorithm requires less ROM size and smaller size module adders compared to those required by existing approaches.

A graph-based approach to finding near-optimal output phase assignments for PLA minimization is presented. A distinctive feature of the approach is that it exploits the necessary and sufficient conditions to reduce the number of product terms needed for PLA implementation and permits the use of existing graph algorithms to solve the PLA output phase optimization problem. The work is based on the transformation of a PLA into a graph whose vertices are the set of conditions required to reduce each product term of the PLA, and whose edges represent the relations between these conditions. Cliques (completely connected subgraphs) in the graph correspond to the output phase assignments required to reduce the product terms represented by the vertices in the cliques. The optimal PLA output phase assignment problem is then formulated as the well-studied problem in graph theory: finding maximum cliques in graphs. Using an existing algorithm for locating cliques in graphs, a modified greedy algorithm is proposed to compute output phase assignments for logic functions in polynomial time. Experimental results using a number of benchmark functions show that the graph-based approach can achieve optimal or near-optimal output phase assignment for PLA minimization and can lead to PLA's with fewer product terms than achieved using existing approaches. >

A new fault simulation method, deductive critical path tracing (D-CPT), for very large combinational circuits is proposed. The simulator uses both the deductive fault propagation technique (used in deductive fault simulation (DFS)) and the critical path tracing (CPT) method in forming the D-CPT. Deductive fault propagation is not performed on the whole fault set of a circuit as in DFS but instead only on a partial fault set, i.e., those faults on fanout stems. The capture lines of each fanout fault are determined, and used to resolve the difficulty in determining the criticality of a fanout stem during the CPT process. Furthermore, the huge storage requirement of DFS is sharply reduced to an acceptable level when handling very large circuits. Experiments on ISCAS benchmark circuits show that the proposed method is both efficient and complete.

Hierarchical interconnection networks (HINs) employ multiple levels in which Lower-level networks provide local communication while higher-level networks facilitate remote communication. HINs are cost effectiveness and fault-tolerant. They can be classified into two classes. The first class includes HINs that are constructed using nodes and/or links replication. The second class uses standby interface nodes. This paper provides performance comparison of HINs in terms of network degree, diameter, cost and packing density. The outcome of this study shows that the Root-Folded Heawood (RFH) and the Flooded Heawood (FloH) provide the best network cost, defined as the product of network diameter and degree. The study also shows that HFCube(n, n) provide the best packing density, i.e. the smallest chip area required for VLSI implementation.

Hierarchical interconnection networks (HINs) provide a framework for designing networks with reduced link cost by taking advantage of the locality of communication that exists in parallel applications. HINs employ multiple levels. Lower-level networks provide local communication while higher-level networks facilitate remote communication. HINs provide fault tolerance in the presence of some faulty nodes and/or links. Existing HINs can be broadly classified into two classes. those that use nodes and/or links replication and those that use standby interface nodes. The first class includes Hierarchical Cubic Networks, Hierarchical Completely Connected Networks, and Triple-based Hierarchical Interconnection Networks. The second HINs class includes Modular Fault-Tolerant Hypercube Networks and Hierarchical Fault-Tolerant Interconnection Network. This paper presents a review and comparison of the topological properties of both classes of HINs. The topological properties considered are network degree, diameter, cost and packing density. The outcome of this study show among all HINs two networks that is, the Root-Folded Heawood (RFH) and the Flooded Heawood (FloH), belonging to the first HIN class provide the best network cost, defined as the product of network diameter and degree. The study also shows that HFCube(n,n)provide the best packing density, that is, the smallest chip area required for VLSI implementation.

Optimizing the number of transistors in a complex MOS gate, which is important for minimizing chip area and delay in VLSI designs, is an NP-complete problem. The worst-case computational complexity of graph-oriented algorithms used in existing approaches is exponential in the number of transistors. This problem is addressed through the use of bridging switches. A theory and an algorithm for optimization of MOS switch networks using an edge-merging technique are proposed. The worst-case computational complexity of the heuristic algorithm proposed is O(n/sup 5/e/sup 2/), where n is the number of nodes and e is the number of edges in the switch network. >

A checker/corrector system has stronger fault-tolerant ability than a checker system. The design of a totally self-checking checker/corrector (TSC3) circuit is considered. The TSC property for checker/corrector systems is defined. One of the critical issues in designing a TSC3 is that the test vectors for detecting the faults in the corrector may not occur in normal operation. A self-exercising method to solve this problem is proposed. A design of self-exercising TSC3 for a two-dimensional error-correcting code is given as an example.

A 2-bit decoder programmable logic array (PLA) is an array of transistors that realizes the sum of products (realized by rows of transistors) of inputs taken from the outputs of 2-input 4-output decoders. Functions of several variables, which are assigned to the decoder inputs using Tomczuk and Miller's heuristic algorithm to pair closely related variables using the autocorrelation of the functions, are realized using reduced area PLAs. The number of product rows (representing product terms) used in such PLAs, which is a function of the assignment of pairs of variables to the decoders, is reduced using simulated annealing techniques which are applied to permuting the assignment of input variables to the decoder inputs.

A new structure is proposed for the realization of multiple-valued logic (MVL) functions. Multiple-valued logic levels are represented in terms of current values, which represent the inputs and the outputs of the MVL circuits. Binary voltage signals are generated inside the structure by using a circuit element called threshold. Using these voltage signals and binary operators, such as AND, OR, XOR and inverter, binary voltage signals are obtained and used as control signals for generating the output current levels for the desired MVL function. The realizations of some example MVL circuits using the proposed structure are included along with HSPICE transient analysis simulation results to verify the functionality of the designed circuits.

A CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed. The set consists of literal, cycle, complement of literal, complement of cycle, min, and tsum operators. In all of the circuits, multiple-valued logic levels are represented in terms of current values. Binary voltage signals are generated inside the circuits using a threshold circuit element. These binary voltage signals are used to generate control signals for switches to realize appropriate current levels for the desired multiple-valued logic levels. Transient analysis simulations (using HSPICE) to verify the functionality of the designed circuits and the effect of variation in process parameters are also reported. >

For pt. I see ibid vol. 40, no. 8 p 503-14 (1993). The performance of the set of operators proposed in pt. I is compared with existing sets of operators for the realization of multiple-valued logic (MVL) functions. In pt. I, a set of operators was proposed consisting of literal, cycle, complement of literal, complement of cycle, min, and tsum operators (Set 1). This set of operators is compared to two existing sets of operators consisting of literal, complement of literal, min, and tsum operators (Set 2) and literal, min, and tsum operators (Set 3). For 3-valued 2-variable MVL functions, it is shown that the maximum number of product terms (PTs) required to realize all functions can be reduced to three PTs (using the Set 1 operators) from five PTs (using the Set 2 operators) and six PTs (using the Set 3 operators). In addition, it is shown that the average number of PTs required to realize all the functions reduces to 2.61 (using the Set 1 operators) from 3.19 (using the Set 2 operators) and 3.61 (using the Set 3 operators). It is anticipated that similar improvements are possible for higher valued logic. Realizations of a 4-valued 2-variable function based on different sets of operators are included to support such a claim. >

The use of programmable logic array structures for the implementation of multi-valued multi-threshold (MVMT) functions using charge-coupled device technology is considered. Two new such structures for the implementation of MVMT functions are introduced. The number of functions realized using these structures is shown to be larger than those realized using previously proposed structures. The new structures are dynamically reprogrammable at the user level by controlling the thresholds of the gates used. One of the proposed structures is superior to the other in terms of the number of functions realized per one column. However, this increase in functionality is achieved at the expense of increasing the number of gates per column by 50%.

A new way for synthesizing MVL functions by injecting pseudo minterm has been proposed in [13]. In this paper, we explore the idea of injecting multiple connected pseudo minterms as a means for reducing the number of implicants needed to synthesize an MVL function. A set of randomly generated 50000 2-variables 4-valued and 50000 2-variables 5-valued functions is used as benchmark. Comparisons made using the obtained results using the same benchmark show that the proposed algorithms improve the performance of technique proposed in [13] in terms of the average number of product terms needed to synthesize a given MVL function. The improvement in the number of PT is achieved at the expense of adding the MUX at the output which adds moderately to the cost of the circuit needed.

A binary-to-quaternary encoder and quaternary-to-binary decoder circuit pair is proposed. Two non-zero voltage levels and two pulse durations are used to define a 4-valued logic scheme. We have simulated the encoder and decoder circuits using model parameters for standard CMOS technology and minimum geometry devices. An average amplitude decoder delay of 10 ns has been recorded using Hspice simulator transient analysis. Width decoder delays of respectively 50 and 75 ns for the rising and the trailing transitions of the encoded signal have been recorded. Since only two voltage levels have to be distinguished, the noise immunity and logic level tolerances are improved, compared to the case where four different voltage levels have to be distinguished using existing approaches. This improvement is achieved at the expense of the greater bandwidth needed for transmission of signals using the proposed scheme.

Programmable logic array (PLA) structures are investigated for the implementation of multi-valued multi-threshold functions using charge-coupled device technology. A new PLA structure is introduced for this purpose. It is shown that the number of functions realized using this structure is larger than those realized using an existing PLA structure. The new structure exhibits the desirable feature of being dynamically reprogrammable at the user level by controlling the thresholds of the gates used.

Algorithms for synthesis of four-valued one- and two-variable functions for CCD (charge coupled device) implementation are proposed. One-variable synthesis is based on the observation that the cost of a realization of a function f(x) increases in the presence of breaks, or negative transitions, in the value of f as x increases. The function is decomposed to minimize the number of such transitions. Two-variable functions are synthesized as a sum of products of literals, taking advantage of literals that are easily implemented in CCD technology. It is concluded that the proposed algorithms perform better than those published previously. >

Application of multi-valued (non-binary) digital signals can provide considerable relief for a number of problems faced in binary systems, such as increased functional density and interconnection wirings. Heuristics have been used to synthesize multiple-valued logic (MVL) functions using near optimal number of product terms. In this paper, we explore the use of particle swarm optimization algorithm for synthesis of MV functions. The proposed approach was tested against 50000 randomly generated 2-variable 4-valued functions. The results show that the proposed algorithm outperforms other deterministic and ant colony based approaches in terms of the average number of product terms needed to synthesize a given MVL function.

The cost effectiveness of using an overflow circuit for truncated difference operation and a metal line for charge replication in the charge-coupled device (CCD) realization of multivalue multithreshold (MVMT) functions is considered. It is shown that the use of these two circuits leads to improved realizations compared to those achieved by previous approaches. >

In this paper, weighted and ordered direct cover algorithms (abbreviated as WDC and ODC, respectively) for synthesis of multiple-valued logic (MVL) functions are proposed. The algorithms are tested using 50000 randomly generated 2-variable 4-valued and 2-variable 5-valued functions. The results obtained are compared to those obtained using existing direct cover techniques. We show that the proposed approaches outperform other existing direct cover based techniques in terms of the average number of product terms required to realize a given MVL function.

Multiple-Valued Logic (MVL) has been used in the design of a number of logic systems, including memory, multi-level data communication coding, and a number of special purpose digital processors. Several algorithms have been proposed in the literature for synthesis of multiple valued logic functions. None of these algorithms provides absolute optimum results for synthesis of these functions. The search space is too large to be explored by deterministic algorithms. In this paper, a Genetic Algorithm based algorithm for synthesis of MVL functions is proposed. The algorithm is tested using 200 randomly generated 2-variable 4-valued functions. The results obtained show that the introduced algorithm outperforms the deterministic technique based on the direct cover approach [3] in terms of the average number of product terms required to realize a given MVL function.