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Trabajo presentado en la International 16th Conference on Nanostructured Materials, NANO 2022, celebrada en Sevilla (España), del 6 al 10 de junio de 2022, Resistive random-access memories (RRAM) hold promise for developing future information technologies with ultra-high storage densities to process unprecedented amounts of data. RRAM operation relies on the formation (set) and rupture (reset) of nanoscale conductive filaments (CFs) with diameters as low as few nanometers in the switching layer. These filaments carry enormous power densities (>1013 W/cm3) that result in high localized temperatures. The heating behavior of these filaments lies at the heart of this technology but little is known experimentally about it. Understanding the temperature of nanoscale filamentary hot spots is key to developing more energy-efficient devices and avoiding thermal cross-talk in future dense RRAM arrays. In this work we report the first thermal measurements of single filament switching in RRAM. For that purpose, we use calibrated scanning thermal microscopy (SThM). This technique allows thermal metrology at sub-50 nm dimensions. We use SThM to locate such filaments in HfO2 RRAM devices with nanoscale resolution and determine the hot spot temperature at the top surface during operation. Then, we match the temperature profile with finite element simulations, using the filament diameter and the thermal boundary conductance at the filament-top electrode interface as fitting parameters, assuming diffusive transport in the filament. We use both conventional (metal) and novel (graphene) top electrodes to assess the effect of heat spreading in memory devices. Our study reveals that a CF of 4 nm with TiN top electrode and 13 nm with single layer graphene as top electrode at power ~100 ¿W can lead to a temperature rise as high as ~1100 K above ambient temperature. We solve a fundamental yet elusive problem that has existed in the data storage community for two decades, i.e. imaging the spatial extent and temperature of the filament operation in metal-oxide-based RRAM. Based on the information provided by the SThM measurement, thermal engineering approaches could be applied to develop energy efficient devices. As an example, one could choose electrodes with a thermal boundary conductance that is low at the filament electrode interface to confine the CF heating, and high at the surrounding oxide interfaces to minimize the lateral heat spreading. Overall, these results advance our knowledge of RRAM engineering for digital storage vs analog computing, our understanding of breakdown in insulators, and showcase a unique application of the SThM technique with ramifications much beyond memory technology.

Trabajo presentado en la International 16th Conference on Nanostructured Materials, NANO 2022, celebrada en Sevilla (España), del 6 al 10 de junio de 2022, Vanadium dioxide (VO2) is widely studied for its prominent insulator-metal transition (IMT) near room temperature, with potential applications in novel memory devices and brain-inspired neuromorphic computing. In previous work of our group, Rana et al. observed multiple intermediate stable resistive states between the insulating and metallic states in VO2 films by tailored temperature sweeps or external electrical stimuli1 . The existence of these intermediate resistive states is particularly attractive for reconfigurable electronic circuitry. In this work, we fabricated planar bridge-structure devices from VO2 thin films, which were grown on TiO2 (001) substrates by pulsed laser deposition (PLD). Traditionally, under voltage/current sweeps, Joule heating in the device triggers the IMT. The switching power depends on the device dimensions. However, in our devices, intermediate steps can happen during the reset when tuning the voltage under a high compliance current. This unique measurements can allow multistate memory within one VO2-based memory cell (in our demonstration 3 bits per cell) and reliable multilevel operation 2 . In order to exploit these intermediate states, we also fabricated devices with two identical parallel VO2 bridges with varying bridge-to-bridge distances. Depending on the bridge distance, we obtain a higher degree of control for the intermediate states. The switching behavior of these bridges depend ultimately on heat dissipation effects. To develop optimum device designs, we carried out nanoscale thermal mapping of in operando devices with varying bridgeto-bridge distances using Scanning Thermal Microscopy (SThM). The concept can readily be extended to more parallel channels and complex network configurations. Moreover, one may further use multilayering to stack bridges in the vertical direction and provide a further dimension for multibit operations

Resumen del trabajo presentado en la 16th International Conference on Nanostructured Materials NANO 2022, celebrada en Sevilla (España), del 6 al 10 de junio de 2022, Self-heating and localized temperatures play an important role in the principle of operation of nano- and micro-scale devices. On the one hand, heating in transistor devices affects the mobility of the carriers, limiting device performance and lifetime. On the other hand, energy dissipation in memory devices is connected to some drawbacks, like reliability and energy efficiency. Understanding the energy dissipation mechanisms is therefore essential for the evaluation, design and optimization of our electronic devices. Optical techniques, like infrared (IR) or Raman thermometry, can be used to obtain thermal maps of devices but their spatial resolution is diffraction limited, i.e., ~5 µm and ~0.5 µm respectively. Scanning thermal microscopy (SThM) is a scanning probe microscopy technique that allows thermal maps of devices with nanoscale resolution (~50 nm). Therefore, SThM is a promising tool for determining local hot spots and self-heating of different types of devices. In this work, we show how SThM can be employed for the characterization of heat dissipation in nanoelectronics. Our SThM uses a thermo-resistive probe whose electrical resistance varies with temperature. This probe can be used as a nanoscale sensor to map the temperature of devices locally. First, we present challenges associated with the calibration of this probe, which are key to obtaining quantitative measurements of device temperatures. Second, we show how a calibrated SThM system can be used to gain knowledge of the energy dissipation of memory devices. We focus on resistive random access (RRAM) and phase change (PCM) memory devices, which show promise for applications such as non-volatile memory and neuromorphic computing. The SThM thermal maps show the filamentary heating from RRAM devices as well as the Joule heated PCM device, displaying local temperature features. These maps provide insights into device operation, showing how the energy dissipates and offering new routes for developing more efficient switching mechanisms

Trabajo presentado como Seminar at the Institute of Micro and Nanotechnology. Disponible en Youtube: https://www.youtube.com/watch?v=UGtTr4E1JR8, One of the greatest challenges of modern society is related to energy consumption, dissipation and waste. A prominent example is that of integrated electronics, where power dissipation issues have limited their performance. In the first part of my talk, I will discuss energy dissipation in electronics, like in transistors based on 2D materials or resistive random-access memory (RRAM). On the one hand, the use of 2D materials, like MoS2, represent new opportunities for the electronic industry. However, understanding their thermal properties, like the thermal conductivity or thermal boundary resistance, is essential to achieve effective energy dissipation and avoid limited performance due to overheating. On the other hand, knowing the temperature reached by RRAM filaments is key to improve and design more efficient memory devices. However, its experimental characterization has been a long lasting challenge due to the localized heating of the filament at the nanoscale. Additionally, advanced management of the heat that is dissipated by these systems for energy conversion or storage might have a major technological impact. In the second part of my talk, I will present thermal devices that are capable to manage heat in a manner analogous to how electronic devices control electricity. I will give an example of a thermal diode that can be applied for energy storage applications.

Graphene and III-nitride semiconductors are promising materials platforms for the development of high-frequency, high-power electronic devices. Successful integration of these materials, however, requires a detailed understanding of the electrical properties of the graphene/III-nitride interface. In this work, we investigate the interfacial charge carrier transport across the graphene/InAIN interface. We show that at room temperature the leakage current in these devices is well described by the Fowler-Nordheim tunneling relation. Temperature-dependent measurements between 100 K and 400 K, however, show that as temperature decreases, the leakage current increases. This observation cannot be explained by Fowler-Nordheim or other standard conduction mechanisms (thermionic emission, Poole-Frenkel emission, trap-assisted tunneling). It is proposed that device processing, specifically polymer residue contamination, affects the interfacial coupling between graphene and the InAIN substrate, resulting in the observed anomalous current transport. Evidence for such a mechanism is provided by Raman spectroscopy and temperature-dependent atomic force microscopy studies.

Trabajo presentado en el Spring Meeting European Materials Research, celebrado Francia del 22 al 26 de mayo de 2017, In this work, we measure the structural, morphological, compositional, thermal and thermoelectric properties of large-area Si0.8Ge0.2 nanomeshed films manufactured by DC-sputtering of Si0.8Ge0.2 on highly ordered porous alumina matrices [1]. The Si0.8Ge0.2 film replicated the porous alumina structure resulting in nano-meshed films. Very good control of the nanomesh geometrical features (pore diameter, pitch, neck) was achieved through the alumina template, with pore diameters ranging from 294 ± 5nm down to 31 ± 4 nm. The method that we developed is able to provide large areas of nano-meshes in a simple and reproducible way, being easily scalable for industrial applications. Most importantly, the thermal conductivity of the films was reduced as the diameter of the porous became smaller to values that varied from ¿ = 1.54 ± 0.27 W K¿1m¿1, down to the ultra-low ¿ = 0.55 ± 0.10 W K¿1m¿1 value. The latter is well below the amorphous limit, while the Seebeck coefficient and electrical conductivity of the material were retained. These properties, together with our large area fabrication approach, can provide an important route towards achieving high conversion efficiency, large area, and high scalable thermoelectric materials. Using this approach, it is possible to control thermal transport of these films through nano-engineering., Project Nanostructured Highefficiency Thermo-Electric Converters project NANOHITEC 263306. PHOtoacoustic MEasurements of Nanostructures for Thermoelectric Applications (PHOMENTA). National Project Infante 201550E072

Trabajo presentado en el Nanospain, celebrado en San Sebastian (España), del 7 al 10 de marzo de 2017, Thermoelectric materials are able to convert a gradient of temperature in a diference of voltage, or vice versa. In order to improve the thermoelectric efficiency of these materials for actual applications, one of the most studied routes is the reduction in the dimensionality, via nanowire fabrication, for instance. This gives rise to a reduction of the thermal conductivity of the material due to the increase of phonon dispersion in the surface of the nanowires [1]. Another route to decrease the thermal conductivity would be the fabrication of interconnected three-dimensional structures, which could be seen as an intricate net of nanowires with many connection points, which increases the phonon dispersion and thus reduces the thermal conductivty. We will review these kinds of structures along with the latest developments of template assisted electrochemical deposition of thermoelectric materials in three-dimensional templates. In this case, the reduction in thermal conductivity is due to the resulting interconnected three-dimensional structure that enhances the phonon scattering; compared with bulk, thin films or nanowires.

Trabajo presentado en el Nanospain, celebrado en San Sebastian (España), del 7 al 10 de marzo de 2017, The understanding of how the properties of the materials, such as thermal conductivity and electrical conductivity, can be tailored by growing nano-scale structures that affect them, is the main aim of this work. The fabrication of nanowires with diameters down to 12 nm and the recent development of threedimensional nanostructured networks based on the controlled pulsed anodization of aluminum [1] open the possibility of tailoring the properties in a certain range. A review of ways of tailoring different properties of materials through nanostructuration with the aid of porous alumina templates will be presented. For instance, in the case of the thermal conductivity, it has been demonstrated how this parameter can be experimentally changed and measured [2]. Moreover, the understanding of the reasons behind this change and how to control from a theoretical point of view has been also pursued. In the case of electrical conductivity, the effect of topological insulating appears in different materials when they are structured at the nano-scale [3].

Trabajo presentado en el LV Congreso Nacional de la Sociedad Española de Cerámica y Vidrio, celebrado en Sevilla (España), del 5 al 7 de octubre de 2016

Trabajo presentado en el Eurotherm Seminar 108: Nanoscale and Microscale Heat Transfer V, celebrado en Santorini (Grecia), del 26 al 30 de septiembre de 2016

Trabajo presentado en el E-MRS Spring Meeting and Exhibit, celebrado en Lille (Francia), del 2 al 6 de mayo de 2016

Trabajo presentado en el Energy Material Nanotechnology (EMN) Meeting, celebrado en Dubai (Emiratos Árabes), en marzo de 2016

Trabajo presentado en la 14th European Conference on Thermoelectrics (ECT2016), celebrada en Lisboa (Portugal), del 20 al 23 de septiembre de 2016