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The ternary logic has a benefit over the binary logic which provides a secured solution to achieve a trade-off between the area and power of the design. However, from the structure of the ternary Aritmetic Logic Unit (ALU), it is clear that its architecture increases the area, propagation delay, and power consumption. To overcome this drawback, a loopback algorithm is proposed to achieve low power and high throughput Internet of Things (IoT) processors. The loopback algorithm reduces the number of processing stages in multipliers and adders which can significantly reduce area and power dissipation. The proposed 2:1 multiplexer-based approach reduces the need for a decoder and results in low power consumption. The proposed design will be implemented in Xilinx ISE 13.0 and simulation will be done in Modelsim. The modified Ternary ALU (TALU) performs finer than the previous TALU method. The number of registers used in this architecture is reduced by up to 25% than the existing system therefore there is a reduction in power dissipation. [ABSTRACT FROM AUTHOR]

In this paper, carrier reservoir semiconductor optical amplifiers (CR-SOAs) are utilized for the first time in designing an all-optical 2 × 1 multiplexer with enable function, operating at 120 Gb/s. Traditional SOAs face challenges with slow carrier recovery, restricting their application in high-speed scenarios. CR-SOA, with a carrier reservoir near the active region, replenishes carriers quickly, enabling faster gain and phase recovery. For the first time, a 2 × 1 multiplexer with an enable input is proposed, adding flexibility and control for dynamic data routing in optical systems. Basic gates such as AND, OR, and NOT gates have been designed using this multiplexer, with the enable input enhancing their versatility. The performance of the multiplexer and gates is evaluated using metrics like quality factor, extinction ratio, contrast ratio, and eye opening factor. The quality factor is analyzed concerning parameters such as amplified spontaneous emission, data rate, carrier transition time, and injection current. Simulation results confirm the functionality of the 2 × 1 multiplexer and logic gates, demonstrating satisfactory performance at high data rates. [ABSTRACT FROM AUTHOR]

As CMOS technology approaches its physical and technical limits, alternative technologies such as nanotechnology or quantum computing are needed to overcome the challenges of lithography, transistor scaling, interconnects, and miniaturization. This article introduces a novel nanotechnology that uses atomic-scale silicon dangling bonds (ASDB) to create high-performance, low-power, nanoscale logic circuits. DBs are atoms that can form basic logic gates on a silicon surface using a scanning tunneling microscope device. ASDB can also be an alternative to the existing complementary metal oxide semiconductor (CMOS) technology. The article also proposes a new bar-shaped pattern to design gates and logic circuits with ASDB nano tecnolgoy. The bar-shaped pattern improves the reliability of the output, reduces the area and power consumption, and solves the problem of interatomic energy effects of ASDB. The article demonstrates the efficiency of the bar-shaped pattern by implementing two-input gates such as AND, NAND, OR, NOR, XOR, XNOR, and a 2:1 multiplexer with ASDB. The article also uses a powerful tool called SiQAD to simulate and verify the performance of the proposed structures with ASDB. According to the simulation results, the proposed logic gates are more energy efficient, stable, and compact than the previous structures. They consume 35% and 24.34% less energy and have 14.18% more stability, respectively. [ABSTRACT FROM AUTHOR]

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The article considers an International Electrotechnical Commission (IEC) standard digital output current sensor with improved current conversion characteristics and expanded functionality. The results of the study of primary electromagnetic current converters used in the current sensor are presented. It is proposed to combine the functions of converting signals into the digital format of the IEC 61850 standard and the functions of current relay protection in the current sensor. The features of the newly developed sensors are shown, allowing for a significant improvement in the main characteristics of relay protection. [ABSTRACT FROM AUTHOR]

Stochastic computing is a non‐traditional computing approach that utilizes stochastic bitstreams to represent numerical values. This representation enables the implementation of circuits using basic logic gates, named stochastic circuits. This work proposes a versatile architecture with correlated input bitstreams for biased accumulation. The design offers a notable reduction in the reliance on random number generators, resulting in lower hardware costs and higher computing accuracy when compared with the existing designs. Experimental results show that the application of Gaussian smoothing has a reduction in area by at least 45% and an improvement in peak signal‐to‐noise ratio of at least 30%. [ABSTRACT FROM AUTHOR]

This paper continues the research on the circuit synthesis problem for a multiplexer function of logic algebra, which is a component of many integrated circuits and is also used in theoretical study. The exact value of the depth of a multiplexer with select lines in the standard basis is found under the assumption that the conjunction and disjunction gates are of depth 1 and the negation gate is of depth 0; the depth equals if . Thus, it follows from previous results that the exact depth value equals for all positive integers such that either or . Moreover, for , this value equals 2, and for , it equals either or . Similar results are also obtained for a basis consisting of all elementary conjunctions and elementary disjunctions of two variables. [ABSTRACT FROM AUTHOR]

This paper provides an analysis of existing single-digit binary adders from the point of view of their implementation on fans built based on metal-oxide-semiconductor field-effect transistor—MOSFETs. The synthesis of a single-digit adder with a conditional sum is carried out. The considered adders are compared in terms of speed and hardware complexity (by the number of MOSFETs). Adders perform arithmetic operations on numbers. In combination with other logical operations, adders are the core of the circuits of arithmetic logic devices that implement several different operations; they are an integral part of different processors. The most important parameters of adders are their hardware complexity and performance; therefore, many options for single-bit and multi-bit connectors with serial, parallel and combined transmissions have been developed. In the final part, a scheme of a multi-bit adder with consecutive transfers on adders with a conditional sum is given. An example of performing addition operations is given. [ABSTRACT FROM AUTHOR]

This letter presents the design of a microstrip-based diplexer for the applications of the Internet of Things (IoT). By incorporating stub-loaded coupled line resonators, the diplexer achieves significant enhancements in its passband performance. Specifically engineered to operate at precise frequencies of 2.55 and 3.94 GHz, the diplexer demonstrates improved isolation and selectivity through the integration of five transmission poles (TPs). A comprehensive analysis is conducted, evaluating crucial parameters, such as size, insertion loss, return loss, and isolation. The diplexer is fabricated on a compact Rogers Duroid 5880 substrate, and experimental measurements validate its effectiveness, exhibiting a low insertion loss of 0.3 dB at 2.55 GHz and 0.4 dB at 3.94 GHz, in close agreement with simulated predictions. The proposed design, featuring stub-loaded coupled line resonators, showcases highly promising passband characteristics, making it a compelling solution for efficient multiplexing of diverse frequency bands in wireless communication applications within the IoT and network-on-chip (NoC) domains. [ABSTRACT FROM AUTHOR]

Abstract Extensive research is now being conducted on the design and construction of logic circuits utilizing quantum-dot cellular automata (QCA) technology. This area of study is of great interest due to the inherent advantages it offers, such as its compact size, high speed, low power dissipation, and enhanced switching frequency in the nanoscale domain. This work presents a design of a highly efficient RAM cell in QCA, utilizing a combination of a 3-input and 5-input Majority Voter (MV) gate, together with a 2 × 1 Multiplexer (MUX). The proposed design is also investigated for various faults such as single cell deletion, single cell addition and single cell displacement or misalignment defects. The circuit under consideration has a high degree of fault tolerance. The functionality of the suggested design is showcased and verified through the utilization of the QCADesigner tool. Based on the observed performance correlation, it is evident that the proposed design demonstrates effectiveness in terms of cell count, area, and latency. Furthermore, it achieves a notable improvement of up to 76.72% compared to the present configuration in terms of quantum cost. The analysis of energy dissipation, conducted using the QCAPro tool, is also shown for various scenarios. It is seen that this design exhibits the lowest energy dispersion, hence enabling the development of ultra-low power designs for diverse microprocessors and microcontrollers.

Time division SQUID multiplexing is being developed as the TES readout technology for the ATHENA X-ray integral field unit and CMB-S4. Close packing of TDM and dc-biased SQUID components is motivated by chip area constraints but has resulted in significant physical neighbor crosstalk in previous generation chips. We present techniques to reduce physical neighbor crosstalk in both linear and two dimensional (2D) TDM chips as well as measurements of crosstalk in these chips. [ABSTRACT FROM AUTHOR]

In this paper, we present a single nano ring resonator using Annular Photonic Crystal (APC) with ultra-compact size for applications in versatile optical network components. The proposed resonator is designed in the hexagonal lattice, made up of Silicon (Si) planar and annular rods, where the annular rods are filled with Silicon Nitride (Si3N4). Despite being pervasive, the proposed structure operates mostly in the C-band wavelength, providing high resonation, low insertion loss, high contrast ratio, and large bandwidth with low loss comprising a single resonator ring with photonic crystal waveguides. This structure is used to realize several high-performance optical network devices like optical ring resonator, 4 × 2 reversible encoder, 1 × 2 power splitter, and a multiplexer. Several parameters and their performances are optimized for this miniaturized photonic device using Finite Difference Time Domain (FDTD) method. This device works in the quantum regime as a slow light device with a better squeeze factor enabling quantum computing. The proposed nanostructure, having a Quality factor (Q) of 396.05, is highly suitable for optical network applications. [ABSTRACT FROM AUTHOR]

Extensive research is now being conducted on the design and construction of logic circuits utilizing quantum-dot cellular automata (QCA) technology. This area of study is of great interest due to the inherent advantages it offers, such as its compact size, high speed, low power dissipation, and enhanced switching frequency in the nanoscale domain. This work presents a design of a highly efficient RAM cell in QCA, utilizing a combination of a 3-input and 5-input Majority Voter (MV) gate, together with a 2 × 1 Multiplexer (MUX). The proposed design is also investigated for various faults such as single cell deletion, single cell addition and single cell displacement or misalignment defects. The circuit under consideration has a high degree of fault tolerance. The functionality of the suggested design is showcased and verified through the utilization of the QCADesigner tool. Based on the observed performance correlation, it is evident that the proposed design demonstrates effectiveness in terms of cell count, area, and latency. Furthermore, it achieves a notable improvement of up to 76.72% compared to the present configuration in terms of quantum cost. The analysis of energy dissipation, conducted using the QCAPro tool, is also shown for various scenarios. It is seen that this design exhibits the lowest energy dispersion, hence enabling the development of ultra-low power designs for diverse microprocessors and microcontrollers. [ABSTRACT FROM AUTHOR]

Adders are one of the basic arithmetic circuits of any processor, microcomputer, multiplication circuits, etc. Presently, the most substantial areas in the research of VLSI design are area, power, and efficient high-speed circuits. In this paper two new architectures Carry Select Adder (CSLA) using D-latch and CSLA using multiplexers are proposed to reduce the power, delay, and its efficiency is compared with conventional carry select adder (CSLA) and existing literature. Architectural level power reduction is the most important area where it plays a vital role in improving the speed and power of the overall circuit. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm technology node is used for the design and implementation. The values obtained across technology in nm underline the dominance of the proposed adder architectures in terms of delay and energy and area efficiency. For the proposed architectures, the evaluation results show that 60%–75% improvement in delay and 22%–56%in power when compared to other architectures. Proposed architectures shows increment in area but overall are delay product reduces compares to existing designs The proposed CSLA-DLATCH-FIR obtained significant reduction for 16-bits for power (46.4 (µW)), delay (0.66), ADP (359.8 × 10–15), and PDP (30.63 × 10–15). While the proposed CSLA-MUX-FIR has attained substantial performance for power (52.44 (µW)), delay (0.82 ns), ADP (457.392 × 10–15), and PDP (42.9 × 10–15). With the use of this proposed CSLA, a FIR filter was able to significantly reduce its power and delay. [ABSTRACT FROM AUTHOR]

A general cellular circuit of functional and switching elements (CCFSE) is a mathematical model of integral circuits (ICs), which takes into account peculiarities of their physical synthesis. A principal feature of this model distinguishing it from the well-known classes of circuits of gates (CGs) is the presence of additional requirements on the geometry of the circuit which ensure the accounting of the necessary routing resources for IC creation. The complexity of implementation of a multiplexer function of Boolean algebra (FBA) in different classes of circuits has been extensively studied. In the present paper, we give asymptotically sharp upper and lower estimates for the area of a CCFSE implementing a multiplexer FBA of order n. We construct a family of circuit multiplexers of order n of area equal to the halved upper estimate, and provide a method of delivering the corresponding lower estimate. [ABSTRACT FROM AUTHOR]

The design of acoustic multiplexer and demultiplexer circuits using ring resonator cavity on mercury-water phononic crystal platform is proposed in the present paper. We investigate the transmission spectra and pressure distribution for different orders of multiplexer and demultiplexers of the proposed structures. The design of acoustic 2:1/4:1 multiplexer and 1:2/1:4 demultiplexer is numerically investigated in Comsol Multiphysics platform. The design could play a crucial role in phononic integrated circuits that are used in underwater and medical applications. [ABSTRACT FROM AUTHOR]

The quantum-dot cellular automata (QCA) are an alternative nanotechnology for overcoming the drawbacks of traditional CMOS technology. QCA is one of the alternative transistors-less nanotechnologies for the implementation of computational circuits. It can also be used for implementation in molecular and nanoscale structures. In this paper, ultradense and quantum-cost-efficient random access memory (RAM) cell designs have been proposed, which are critical for designing large memory circuits. A novel loop-based RAM cell design using a proposed 2:1 multiplexer (MUX) and a three-input majority gate has been implemented on different quantum-dot cell sizes such as 14 × 14 nm2, 16 × 16 nm2, and 18 × 18 nm2. According to the performance results, the RAM cell design has a 35.89% minimum cell count, a 56.05% small area, and a 16.66% reduction in latency as compared to its existing design. The presented design performance and energy consumption are evaluated by QCADesigner-E 2.2 (coherence vector W/energy) and QCADesigner version 2.0.3 (bistable approximation) and also show the thermal map of the suggested MUX and RAM cell designs at 2 K temperature. [ABSTRACT FROM AUTHOR]

The operation of a four-channel multiplexer, utilizing multimode interference (MMI) wavelength division multiplexing (WDM) technology, can be designed through the cascading of MMI couplers or by employing angled MMI couplers. However, conventional designs often occupy a larger footprint, spanning a few millimeters, thereby escalating the energy power requirements for the photonic chip. In response to this challenge, we propose an innovative design for a four-channel silicon nitride (Si3N4) MMI coupler with a compact footprint. This design utilizes only a single MMI coupler unit, operating within the O-band spectrum. The resulting multiplexer device can efficiently transmit four channels with a wavelength spacing of 20 nm, covering the O-band spectrum from 1270 to 1330 nm, after a short light propagation of 22.8 µm. Notably, the multiplexer achieves a power efficiency of 70% from the total input energy derived from the four O-band signals. Power losses range from 1.24 to 1.67 dB, and the MMI coupler length and width exhibit a favorable tolerance range. Leveraging Si3N4 material and waveguide inputs and output tapers minimizes light reflection from the MMI coupler at the input channels. Consequently, this Si3N4-based MMI multiplexer proves suitable for deployment in O-band transceiver data centers employing WDM methodology. Its implementation offers the potential for higher data bitrates while maintaining an exemplary energy consumption profile for the chip footprint. [ABSTRACT FROM AUTHOR]

In this work, an all-optical compact 2*1 multiplexer gate based on two-dimensional photonic crystals is presented. The structure is made of silicon rods (which are formed in the eight shaped (8) waveguide) in the background of air. The proposed multiplexer is designed based on only linear materials to overcome low gain and nonlinearity difficulties. The functionality of the multiplexer is fulfilled by considering the interference and scattering effects of silicon defect rods situated in the structure. The performance of the presented structure is studied by considering the photonic band gap, field distribution and transmitted power spectra. Plane wave expansion (PWE) and finite-difference-time-domain (FDTD) methods are utilized for extracting the PBG and field distribution diagrams. The dimension (116.64 μm2), contrast ratio (21.39 dB), rise time (0.8 ps) and bitrate (0.312 Tbit/s) are the remarkable specifications of the proposed multiplexer. In other words, compatibility and integrability are the main advantages of the presented structure. As a result, the proposed 2*1 multiplexer can be considered as an appropriate candidate in optical circuits (optical networking and optical signal processing). [ABSTRACT FROM AUTHOR]

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature. [ABSTRACT FROM AUTHOR]

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature.

A wideband signal combining circuit with continuous bandwidth based on multichannel different‐/same‐frequency power combiner is presented. Two‐way signals with the same frequency can be combined to a higher power signal. Two‐way signals with different frequencies can be combined into a broadband signal. A stepped impedance resonator (SIR) is used as a multimode resonator. The wider bandwidth is got by SIR. And the selectivity of the two filtering channels is improved by the introduction of SIR stubs, which generate four transmission zeros on both sides of the passbands. The high 3‐dB point of the low‐frequency channel overlaps with the low 3‐dB point of the high‐frequency channel. Therefore, the output passband is continuous. The measured frequency ranges of two channels are 1.34–2.21 GHz/2.21‐2.87 GHz, respectively, and from 1.46 to 2.74 GHz, the input reflection coefficient is such that the return loss is higher than 15.5 dB. The insertion loss of the two channels is 0.71/1.18 dB, and the measured isolation is higher than 15.4 dB. The measured bandwidth of the combining signal is 1.5 GHz (1.34–2.84 GHz). [ABSTRACT FROM AUTHOR]

A Reversible gate that can be reversed implements a reversible operation and has the same number of inputs and outputs that create a specific 1 to 1 between inputs and outputs. The field of reversible logic is now the center of considerable attention in the scientific community. Due to its capacity to produce digital circuits with low energy consumption, the incorporation of this method into the design of digital circuits has opened up a wide range of possibilities in fields including biotechnology, quantum entanglement, remote sensing, and computing technologies. This paper presents a sophisticated multiplexer circuit based on reversible logic and using many basic reversible gates. The total number of reversible gates used in the circuit and the number of redundant outputs produced are the two main criteria used to assess the multiplexer circuit's optimization. This circuit is highly beneficial for designing digital circuits with reduced power loss and improved performance. [ABSTRACT FROM AUTHOR]

The multiplexer is a combinational circuit that transfers multiple data inputs over a single output line. The input data are selected and transferred to the output line based on the selection line. In this work, 2 × 1 and 4 × 1 multiplexer is proposed. The proposed multiplexer has been worked out using the electro-optic principle. It is implemented using lithium niobate-based Mach–Zehnder interferometer (LN-MZI). LN-MZI is used as an optical switching device. The performance parameters extinction ratio, contrast ratio and insertion loss have been computed and found 31.31, 28.02 and 0.043 dB respectively. [ABSTRACT FROM AUTHOR]

The aim of this paper is to propose a compact device to design a multiplexer and demultiplexer which can reduce the circuit area while maintaining competitive performance. A novel device, the dielectric-separated independent-gate junctionless transistor (DSIG-JLT), is used to implement functional logic of a multiplexer and demultiplexer. The DSIG-JLT has four gates that can be electrically controlled in multiple ways to realize different digital logics. The DSIG-JLT is used to realize a 2 × 1 multiplexer and 1 × 2 demultiplexer by two different logic styles. The 2 × 1 multiplexer is implemented using four transistors, and the 1 × 2 demultiplexer is implemented using five transistors by NAND logic (logic style-1). Further, by using mixed logic, the 2 × 1 multiplexer is designed using three transistors, and the 1 × 2 demultiplexer using four transistors (logic style-2). A 4 × 1 multiplexer is also implemented using eight transistors. The propagation delay, rise time, and fall time of the 2 × 1 multiplexer (logic style-1) are calculated and are found to be 24.45 ps, 31 ps, and 8.2 ps, respectively, at a supply voltage (VDD) of 1 V. It is found that with a change in supply voltage from 0.7 to 1.0 V, the delay, rise time, and fall time decrease by 17.2%, 11.4%, and 65.69%, respectively. Simulations are carried using the ATLAS 3D device simulator in mixed mode. [ABSTRACT FROM AUTHOR]

In this paper, a probe for measuring radio-frequency electric fields in the environment is designed and presented. These electric fields consist of multi cellular technology (2G, 3G and 4G), including four bands: GSM900, GSM1800, 3G2100 and LTE2600. This device, called the MCT electric probe, is realized by three orthogonal antennas, in connection to frequency multiplexer circuits and detectors. The proposed antenna is a 3-D multi-branch monopole antenna, and these orthogonal antennas can receive the electric fields in all directions uniformly and isotopically. The proposed multiplexer can separate the received signals into four narrowband and has the ability to remove out-of-band signals. The detector is able to convert the fields received from the antenna and multiplexer sections to suitable DC voltages for amplifying and digital processing. Finally, the designed MCT electric probe is fabricated and tested. The measurements confirm the proper operation of the probe in terms of dynamic range, accuracy, sensitivity, and the linearity and isotropicity of the received electric fields.

This paper provides an analysis of existing single-digit binary adders from the point of view of their implementation on fans built based on metal-oxide-semiconductor field-effect transistor—MOSFETs. The synthesis of a single-digit adder with a conditional sum is carried out. The considered adders are compared in terms of speed and hardware complexity (by the number of MOSFETs). Adders perform arithmetic operations on numbers. In combination with other logical operations, adders are the core of the circuits of arithmetic logic devices that implement several different operations; they are an integral part of different processors. The most important parameters of adders are their hardware complexity and performance; therefore, many options for single-bit and multi-bit connectors with serial, parallel and combined transmissions have been developed. In the final part, a scheme of a multi-bit adder with consecutive transfers on adders with a conditional sum is given. An example of performing addition operations is given.

Following the considerable development of big data and the need for real-time information processing, the recent computing paradigm changed from centralized intelligence on cloud computing to the distributed intelligence on Edge Computing. On the algorithm layer, Artificial Intelligence (AI) has been applied in different areas related to intelligent-edge applications. In this type of application, consumption and speed present essential challenges when designing hardware-level architecture on the embedded systems. In particular, an Edge Computing System (ECS) must be an energy efficient, compact, and fast component integrated into edge devices. Miniaturization has been happening at a steady pace for the last years. However, the MOS transistor size has been slowly reaching the physical limit. In this paper, we propose a Quantum Cellular Automata clock-phase-based technique for the design of the proposed ALU module. The obtained results using the QCA architecture designer exhibit better performances over the existing designs in terms of size, cell number, cost, latency, and power consumption. We have also used QCAPro software for power consumption estimation. The results show the effectiveness of the design in terms of cost and power. [ABSTRACT FROM AUTHOR]

In this paper, a high-performance priority encoder of the 2-dimensional array is investigated and modified. This work involves 64-bit priority encoder design and verification using Verilog and cadence virtuoso. For the Verilog code, Vivado has been used for the Artix-7 FPGA board. For Cadence virtuoso, GPDK 180 nm CMOS technology has been used. By using a reduced 2-D priority encoder, 1000 transistors have been saved. Due to this, the delay of the whole 64-bit priority encoder is reduced by 62.17% as compared to PE64 and 61.68% as compared to modified PE64. [ABSTRACT FROM AUTHOR]

In this paper, a probe for measuring radio-frequency electric fields in the environment is designed and presented. These electric fields consist of multi cellular technology (2G, 3G and 4G), including four bands: GSM900, GSM1800, 3G2100 and LTE2600. This device, called the MCT electric probe, is realized by three orthogonal antennas, in connection to frequency multiplexer circuits and detectors. The proposed antenna is a 3-D multi-branch monopole antenna, and these orthogonal antennas can receive the electric fields in all directions uniformly and isotopically. The proposed multiplexer can separate the received signals into four narrowband and has the ability to remove out-of-band signals. The detector is able to convert the fields received from the antenna and multiplexer sections to suitable DC voltages for amplifying and digital processing. Finally, the designed MCT electric probe is fabricated and tested. The measurements confirm the proper operation of the probe in terms of dynamic range, accuracy, sensitivity, and the linearity and isotropicity of the received electric fields. [ABSTRACT FROM AUTHOR]

Mode multiplexers/demultiplexers (MUX/deMUX) are key components in mode division multiplexing. A silica waveguide mode MUX consisting of four cascaded directional couplers is experimentally demonstrated. The beam propagation method is used in the device design and optimization. Thermal oxidation, plasma-enhanced chemical vapor deposition, and ultraviolet photolithography are adopted in the silica waveguide mode MUX fabrication. The measurement results prove that the input E00 mode can be selectively converted to E10 mode, E20 mode, and E30 mode. Within the wavelength range of 1500 to 1620 nm, the insertion loss is less than 12.2 dB. The proposed mode MUX has good potential in on-chip MDM applications. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata is pioneering nanotechnology, which has gained attention amongst the research community as a solid potential substitute against complementary metal oxide semiconductor (CMOS) technology. This paper explores a unique loop-based random-access memory (RAM) circuit with an asynchronous set and resets by utilizing an innovative (2 × 1) multiplexer and a D-latch in the design. Efficient designs of (1 × 4) RAM and (4 × 4) RAM, structured in three-layer, are implemented. The proposed multilayer designs are improved up to 20–30% over the existing single-layer and multilayer designs in terms of the total number of cells counts, area, latency, and overall cost. The proposed (4 × 4) RAM and (m × n) RAM structures show the excellent scalability of the projected RAM cells in designing complex circuits. The simulation results have been obtained, and their accuracy has been checked using QCADesigner 2.0.3 tool. [ABSTRACT FROM AUTHOR]

The operation of a four-channel multiplexer, utilizing multimode interference (MMI) wavelength division multiplexing (WDM) technology, can be designed through the cascading of MMI couplers or by employing angled MMI couplers. However, conventional designs often occupy a larger footprint, spanning a few millimeters, thereby escalating the energy power requirements for the photonic chip. In response to this challenge, we propose an innovative design for a four-channel silicon nitride (Si3N4) MMI coupler with a compact footprint. This design utilizes only a single MMI coupler unit, operating within the O-band spectrum. The resulting multiplexer device can efficiently transmit four channels with a wavelength spacing of 20 nm, covering the O-band spectrum from 1270 to 1330 nm, after a short light propagation of 22.8 µm. Notably, the multiplexer achieves a power efficiency of 70% from the total input energy derived from the four O-band signals. Power losses range from 1.24 to 1.67 dB, and the MMI coupler length and width exhibit a favorable tolerance range. Leveraging Si3N4 material and waveguide inputs and output tapers minimizes light reflection from the MMI coupler at the input channels. Consequently, this Si3N4-based MMI multiplexer proves suitable for deployment in O-band transceiver data centers employing WDM methodology. Its implementation offers the potential for higher data bitrates while maintaining an exemplary energy consumption profile for the chip footprint.

Ion-sensitive field-effect transistors (ISFETs) are used as elementary devices to build many types of chemical sensors and biosensors. Organic thin-film transistor (OTFT) ISFETs use either small molecules or polymers as semiconductors together with an additive manufacturing process of much lower cost than standard silicon sensors and have the additional advantage of being environmentally friendly. OTFT ISFETs' drawbacks include limited sensitivity and higher variability. In this paper, we propose a novel design technique for integrating extended-gate OTFT ISFETs (OTFT EG-ISFETs) together with dual-gate OTFT multiplexers (MUXs) made in the same process. The achieved results show that our OTFT ISFET sensors are of the state of the art of the literature. Our microsystem architecture enables switching between the different ISFETs implemented in the chip. In the case of sensors with the same gain, we have a fault-tolerant architecture since we are able to replace the faulty sensor with a fault-free one on the chip. For a chip including sensors with different gains, an external processor can select the sensor with the required sensitivity. [ABSTRACT FROM AUTHOR]

Terahertz (THz) band, which owns abundant and underexplored frequency spectrum, has provided rich scientific and technological opportunities in numerous research fields, such as radio astronomy, atmospheric science and high‐speed communication. As one of the key components in THz systems, the multiplexer cannot only separate/combine different bands, but can also promote the development of THz instruments toward wider band and more multibands. Thanks to the high‐precision computer numerical control milling and micromachining technologies, a lot of THz waveguide multiplexers have been reported in recent years. According to the classification of design configurations, this article offers a brief overview on the developed THz multiplexers. In addition, the performance and system applications of different waveguide‐typed multiplexers are discussed. Therefore, this review will provide a valuable reference for the further development of THz waveguide multiplexers with high performance. [ABSTRACT FROM AUTHOR]

The work considers controversial problems with the introduction of specialized and at the same time universal large integrated circuits, which are clarified at the initial stages of automated hierarchical design. Universal micro- and nanocircuits with configurable logic are created in the article to increase the efficiency of automated design systems. The article provides effective methods of programming multiplexer micro- and nanocircuits with configured logic for implementing Boolean and majority logic functions. The obtained results are used to configure the multiplexer functional blocks. With the help of modern automated design systems, comparative modeling of logic micro- and nanocircuits with configured logic was performed, which proved the adequacy of their functioning, the advantages of frequency and disadvantages of temperature characteristics of nanomultiplexer circuits. [ABSTRACT FROM AUTHOR]

Low power demand of electronics industry and communication systems are driven by technology scaling and marketing. Compressors are the most often used modules in the architecture of an Arithmetic Circuits. Compressor is the basic combinational digital logic circuit for performing numerous arithmetic operations. The design criterion in any Compressor circuit involves the XOR-XNOR and multiplexer circuits. It is a prominent component in the designing of integrated circuit that performs arithmetic operations. The proposed Compressor is design in order to reduce the transistor count which results in curtailing power dissipation and delay. The performance parameter are recorded and tabulated. This compressor has less delay and low power dissipation. The temperature effect has also shown a linear change in power dissipation in lower temperature ranges which shows the robustness of the proposed circuits. The proposed compressor can be used in numerous applications such as multiplier, DSP microprocessor and data processing systems. [ABSTRACT FROM AUTHOR]

The general focus of this work is to design an area-optimised full adder and utilise it to lay out a low-power arithmetic unit that can be helpful for microprocessors. A traditional full adder with 28 transistors has been devised with 10 transistors of an equal amount of PMOS and NMOS, guaranteeing the proper switching activity. The proposed full adder has one XOR gate and two 2:1 multiplexers in which the XOR gate has been customised with 4 transistors using pass transistor logic (PTL). In contrast, the gate diffusion input (GDI) technique has been used to alter the multiplexer design. The combination of the GDI and PTL brings a novelty to the full adder circuit, through which the design required only 10 transistors to perform adding operations. The proposed full adder design has been constructed against ten different complementary metal oxide semiconductor processing technologies, namely 0.6 µm, 0.8 µm, 0.12 µm, 1.2 µm, 0.18 µm, 0.25 µm, 0.35 µm, 50 nm, 70 nm and 90 nm. Pre- and post-layout simulations evidence the accuracy of the results in which the design consumes 1.843 µW of power with 0.605 ns as the worst-case delay on 90 nm technology. Further, the full adder has been extended as an adder/subtractor unit of 4 bits, with the power delay product as 0.1285 × 10− 18 J for the critical delay of 1.095 ns. The proposed design has been compared against the various full and approximate adders. The full adder has a 12.99% power reduction over the existing low-power adder and a 58.4% power reduction over the 28 transistors. This ensures that the proposed adder outperforms the traditional design and the state of the artwork. [ABSTRACT FROM AUTHOR]

Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over binary reversible logic. Multiplexer and demultiplexer circuits are crucial parts of computing circuits in ALU, and their efficient design can significantly affect the processors’ performance. A new scalable realization of quaternary reversible $4\times 1$ multiplexer and $1\times 4$ demultiplexer, based on quaternary 1-qudit Shift, 3-qudit Controlled Feynman, and 2-qudit Muthukrishnan-Stroud gates, is presented in this paper. Moreover, the corresponding generalized quaternary reversible $n\times 1$ multiplexer and $1\times n$ demultiplexer circuits are proposed. The comparison, with respect to the current literature, shows that the proposed circuits are more efficient in terms of quantum cost, the number of garbage outputs, and the number of constant inputs.