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A multiple chip magnetic bubble memory cell design developed for NASA embodies the low power, low weight, environmental tolerance and reliability necessary for successful operation in spacecraft launch and mission environments. Packaging of multiple chips in a common magnetic bias, drive coil assembly reduces weight and volume overhead per chip and also reduces the number of coil drive components required. This 8 x 10 to the 5th bit cell is conduction cooled and provides a metal and ceramic sealed hermetic chip environment.

The results are summarized of a program to demonstrate the feasibility of Bubble Domain Memory Technology as a mass memory medium for spacecraft applications. The design, fabrication and test of a partially populated 10 to the 8th power Bit Data Recorder using 100 Kbit serial bubble memory chips is described. Design tradeoffs, design approach and performance are discussed. This effort resulted in a 10 to the 8th power bit recorder with a volume of 858.6 cu in and a weight of 47.2 pounds. The recorder is plug reconfigurable, having the capability of operating as one, two or four independent serial channel recorders or as a single sixteen bit byte parallel input recorder. Data rates up to 1.2 Mb/s in a serial mode and 2.4 Mb/s in a parallel mode may be supported. Fabrication and test of the recorder demonstrated the basic feasibility of Bubble Domain Memory technology for such applications. Test results indicate the need for improvement in memory element operating temperature range and detector performance.