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1. A New Direct Measurement Method of Time Dependent Dielectric Breakdown at High Frequency

2. Impact of gate impedance on dielectric breakdown evaluation for 28 nm FDSOI transistors

3. Middle of the Line Dielectrics Reliability and Percolation Modelling through 65nm to 28nm Nodes

4. Moisture Diffusion in Dense SiO2 and Ultra Low k Integrated Stacks

5. Temperature dependence of TDDB at high frequency in 28FDSOI

6. New perspectives in defect centric model for NBTI reliability

7. New Insights on device level TDDB at GHz speed in advanced CMOS nodes

8. Impact of Passive & Active Load Gate Impedance on Breakdown Hardness in 28nm FDSOI Technology

9. On the cumulative distribution function of the defect centric model for BTI reliability

10. FDSOI Mosfet gate dielectric breakdown Vd dependancy

11. New NBTI models for degradation and relaxation kinetics valid over extended temperature and stress/recovery ranges

12. Process optimization for HCI improvement in I/O analog devices

13. A new method for quickly evaluating reversible and permanent components of the BTI degradation

14. AC TDDB extensive study for an enlargement of its impact and benefit on circuit lifetime assessment

15. Modeling self-heating effects in advanced CMOS nodes

16. NEW INSIGHTS ON STRAINED SIGE CHANNELS PFET NBTI RELIABILITY

17. Improved analysis of NBTI relaxation behavior based on fast I–V measurement

18. Gate stack solutions in gate-first FDSOI technology to meet high performance, low leakage, VT centering and reliability criteria

19. Characterization and modeling of NBTI permanent and recoverable components variability

20. Layout Dependent Effect: Impact on device performance and reliability in recent CMOS nodes

21. Unified Compact Model of Soft Breakdown Oxide Degradation and Its Impact on CMOS Circuits Reliability

22. Challenges and opportunity in performance, variability and reliability in sub-45nm CMOS technologies

23. Process dependence of BTI reliability in advanced HK MG stacks

24. Performance and reliability of advanced High-K/Metal gate stacks (Invited Paper)

25. Universal Correlation Between Mobility and NBTI on Advanced High-k/Metal Gate Stacks

26. Reliability issues for nano-scale CMOS dielectrics

27. Physical understanding of low frequency degradation of NMOS TDDB in High-k metal gate stack-based technology. Implication on lifetime assessment

28. Performance and reliability of strained SOI transistors for advanced planar FDSOI technology

29. New Insights Into Oxide Breakdown Current Partitioning Analysis for MOS Devices

30. Application of a TDDB Model to the Optimization of the Programming Voltage and Dimensions of Antifuse Bitcells

31. Frequency dependence of TDDB & PBTI with OTF monitoring methodology in high-k/metal gate stacks

32. 14nm FDSOI technology for high speed and energy efficient applications

33. Experimental analysis of defect nature and localization under hot-carrier and bias temperature damage in advanced CMOS nodes

34. New insight on the frequency dependence of TDDB in high-k/metal gate stacks

35. Foundations for oxide breakdown compact modeling towards circuit-level simulations

36. New insight on high-k/metal gate reliability modeling for providing guidelines for process development

37. Interaction between BTI and HCI degradation in High-K devices

38. Dielectric breakdown in high-K metal gate: Measurement, device level model and application to circuit

39. 28nm node bulk vs FDSOI reliability comparison

40. New insights into gate-dielectric breakdown by electrical characterization of interfacial and oxide defects with reverse modeling methodology

41. Impact of backside interface on Hot Carriers degradation of thin film FDSOI Nmosfets

42. On the understanding of the effects of high pressure deuterium and hydrogen final anneal

43. Mean time to failure distribution in thin oxide film: Observation at nano and devices scale and modelling using a filamentary growth model

44. Mosfet's hot carrier degradation characterization and modeling at a microscopic scale

45. Low cost wafer level parallel test strategy for reliability assessments in sub-32nm technology nodes

46. Oxide defects generation modeling and impact on BD understanding

47. SiON and SiO2/HfSiON gate oxides time dependent dielectric breakdown measurements at nanoscale in ultra high vacuum

48. PBTI mechanisms in La containing Hf-based oxides assessed by very Fast IV measurements

49. Multiple microscopic defects characterization methods to improve macroscopic degradation modeling of MOSFETs

50. Understanding the influence of antifuse bitcell dimensions the programming time and energy using an analytical model

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