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We present an analog silicon photomultiplier (SiPM) based on a standard 55 nm Bipolar-CMOS-DMOS (BCD) technology. The SiPM is composed of 16$\times$16 single-photon avalanche diodes (SPADs) and measures 0.29$\times$0.32 mm$^2$. Each SPAD cell is passively quenched by a monolithically integrated 3.3 V thick oxide transistor. The measured gain is 3.4$\times$ 10$^5$ at 5 V excess bias voltage. The single-photon timing resolution (SPTR) is 185 ps and the multiple-photon timing resolution (MPTR) is 120 ps at 3.3 V excess bias voltage. We integrate the SiPM into a co-axial light detection and ranging (LiDAR) system with a time-correlated single-photon counting (TCSPC) module in FPGA. The depth measurement up to 25 m achieves an accuracy of 2 cm and precision of 2 mm under the room ambient light condition. With co-axial scanning, the intensity and depth images of complex scenes with resolutions of 128$\times$256 and 256$\times$512 are demonstrated. The presented SiPM enables the development of cost-effective LiDAR system-on-chip (SoC) in the advanced technology.

This work presents a novel InGaAs/InP SPAD structure fabricated using a selective area growth (SAG) method. The surface topography of the selectively grown film deposited within the 70 mu m diffusion apertures is used to engineer the Zn diffusion profile to suppress premature edge breakdown. The device achieves a highly uniform active area without the need for shallow diffused guard ring (GR) regions that are inherent in standard InGaAs/InP SPADs. We have obtained 33% and 43% photon detection probability (PDP) at 1550 nm, with 5 V and 7 V excess bias, respectively. These measurements were performed at 300 K and 225 K. The dark count rate (DCR) per unit area at room temperature and at 5 V excess bias is 430 cps/mu m(2) and it decreases to 5 cps/mu m(2) at 225 K. Timing jitter is measured with passive quenching at 1550nm as 149 ps at full-width-at-half-maximum (FWHM), (300 K, 5 V excess bias). The proposed technology is suitable for a number of applications, including optical time-domain reflectometry (OTDR), quantum information, and light detection and ranging (LiDAR).

This paper presents three different types of on-chip avalanche photodiodes (APDs) realized in a TSMC 180 nm 1P6M RF CMOS process, i.e., a P+/N-well (NW) APD for its high responsivity and large bandwidth by excluding slow diffusion currents; a P+/Deep N-well (DNW) APD for its improved near-infrared (NIR) sensitivity; and a P+/NW/DNW APD for its capability to prevent premature edge breakdown and improve NIR sensitivity. Thereafter, a conventional voltage-mode optoelectronic receiver (V-OER) was realized to confirm the feasibility of the three on-chip APDs. However, the measured results of the V-OER demonstrate a very narrow dynamic range. Therefore, we propose a current-mode optoelectronic receiver (C-OER) realized in the same CMOS process for the applications of short-range LiDAR sensors, where current-conveyor input buffers are exploited to deliver the photocurrents with no significant signal loss to the following inverter cascode transimpedance amplifier, hence resulting in an extended dynamic range. The optically measured results of the C-OER with an 850 nm laser source demonstrate large output pulses. The C-OER chip consumes 47.8 mW from a 1.8 V supply and the core occupies 0.087 mm2.

In this paper, we present the first CMOS SPAD with performance comparable or better than that of the best custom SPADs, to date. The SPAD-based design, fully integrated in 180 nm CMOS technology, achieves a peak PDP of 55% at 480nm with a very broad spectrum spanning from NUV to NIF and a normalized DCR of 0.2cps/m2, both at 6V of excess bias. Thanks to a dedicated CMOS pixel circuit front-end, an afterpulsing probability of about 0.1% at a dead time of3ns were achieved. We designed three SPADs with a diameter of 25, 50, and 100m to study the impact of size on the timing jitter and to create a scaling law for SPADs. For these SPADs, a SPTR of 12.1ps, 16ps, and 27ps was achieved at 6V of excess bias, respectively. The SPADs operate in a wide range of temperatures, from -65C to 40C, reaching a normalized DCR of 1.6 mcps/m2 at 6V of excess bias. The proposed SPADs are ideal for a wide range of applications, including LiDAR, super-resolution microscopy, QRNGs, QKD, fluorescence lifetime imaging, time-resolved Raman spectroscopy, to name a few.

CMOS single-photon avalanche diodes (SPADs) have broken into the mainstream by enabling the adoption of imaging, timing, and security technologies in a variety of applications within the consumer, medical and industrial domains. The continued scaling of technology nodes creates many benefits but also obstacles for SPAD-based systems. Maintaining and/or improving upon the high-sensitivity, low-noise, and timing performance of demonstrated SPADs in custom technologies or well-established CMOS image sensor processes remains a challenge. In this paper, we present SPADs based on DPW/BNW junctions in a standard Bipolar-CMOS-DMOS (BCD) technology with results comparable to the state-of-the-art in terms of sensitivity and noise in a deep sub-micron process. Technology CAD (TCAD) simulations demonstrate the improved PDP with the simple addition of a single existing implant, which allows for an engineered performance without modifications to the process. The result is an 8.8 $\mu$ m diameter SPAD exhibiting $\sim$ 2.6 cps/ $\mu$ m $^2$ DCR at 20 $^{\circ}$ C with 7 V excess bias. The improved structure obtains a PDP of 62% and $\sim$ 4.2% at 530 nm and 940 nm, respectively. Afterpulsing probability is $\sim$ 0.97% and the timing response is 52 ps FWHM when measured with integrated passive quench/active recharge circuitry at 3 V excess bias.

Recent advances in computer-aided detection via deep learning (DL) now allow for prostate cancer to be detected automatically and recognized with extremely high accuracy, much like other medical diagnoses and prognoses. However, researchers are still limited by the Gleason scoring system. The histopathological analysis involved in assigning the appropriate score is a rigorous, time-consuming manual process that is constrained by the quality of the material and the pathologist’s level of expertise. In this research, we implemented a DL model using transfer learning on a set of histopathological images to segment cancerous and noncancerous areas in whole-slide images (WSIs). In this approach, the proposed Ensemble U-net model was applied for the segmentation of stroma, cancerous, and benign areas. The WSI dataset of prostate cancer was collected from the Kaggle repository, which is publicly available online. A total of 1000 WSIs were used for region segmentation. From this, 8100 patch images were used for training, and 900 for testing. The proposed model demonstrated an average dice coefficient (DC), intersection over union (IoU), and Hausdorff distance of 0.891, 0.811, and 15.9, respectively, on the test set, with corresponding masks of patch images. The manipulation of the proposed segmentation model improves the ability of the pathologist to predict disease outcomes, thus enhancing treatment efficacy by isolating the cancerous regions in WSIs.

This article presents a 64 $\times $ 64 indirect time-of-flight (iToF) image sensor with a depth range of 50 m, integrated into a 1P4M 110-nm CMOS process. The sensor is based on a single-photon avalanche diode (SPAD), the range-dependent phase delay of which is measured by compact analog time-gated pulse counters and then read out by column-parallel single-slope (SS) analog-to-digital converters (ADCs). We present two prototypes of iToF sensors that exploit one- or two-tap counters in the pixel. Compared to the one-tap sensor, the two-tap sensor achieves an improved fill factor of 26.3% with a pixel pitch of 32 $\mu \text {m}$ . This improvement is realized by using a retrograde deep n-well as guard-ring structure and two analog counters whose layout has been optimized. By utilizing two different demodulation frequencies of 1.56 and 50 MHz, the two-tap sensor achieves a large depth range of 50 m with a relative depth uncertainty of 0.22% and a high 3-D frame rate of 65 frames/s. When using an optical bandpass filter and multi-frame accumulation, the sensor shows a tolerance of 120-klx sunlight. Compared with the previous iToF benchmarks, the proposed SPAD-based iToF sensor demonstrates the largest depth range without compromising the relative depth uncertainty.

With the recent emergence of artificial intelligence (AI) technology, autonomous vehicle industry has rapidly adopted this technology to investigate self-driving systems based on AI technology. Although autonomous driving is frequently used in high-speed environments, most studies are conducted on low-speed driving on complex urban roads. Currently, most commercialized self-driving cars in SAE autonomous driving level 2 provide practical performance on high-speed roads using various sensors. However, these systems have to process huge sensor data and apply complex control algorithms. Recently, studies have been conducted on the use of image-based end-to-end deep learning to control autonomous driving systems that can be configured at a low cost without expensive sensors and complex processes. In this study, we proposed an autonomous driving control system using a novel end-to-end deep learning model for high-speed environments, and also compared the performance of the proposed system with NVIDIA end-to-end driving system.

This paper presents a single-photon avalanche diode (SPAD) in 55 nm bipolar-CMOS-DMOS (BCD) technology. In order to realize a SPAD having sub-20 V breakdown voltage for mobile applications while preventing high tunneling noise, a high-voltage N-well available in BCD is utilized to implement the avalanche multiplication region. The resulting SPAD has a breakdown voltage of 18.4 V while achieving an excellent dark count rate of 4.4 cps/µm2 at the excess bias voltage of 7 V in spite of the advanced technology node. At the same time, the device achieves a high peak photon detection probability (PDP) of 70.1% at 450 nm thanks to the high and uniform E-field. Its PDP values at 850 and 940 nm, wavelengths of interest for 3D ranging applications reach 7.2 and 3.1%, respectively, with the use of deep N-well. The timing jitter of the SPAD, full width at half maximum (FWHM), is 91 ps at 850 nm. It is expected that the presented SPAD enables cost-effective time-of-flight and LiDAR sensors with the advanced standard technology for many mobile applications.

This article introduces a modular, direct time-of-flight (TOF) depth sensor. Each module is digitally synthesized and features a 2 $\times $ (8 $\times $ 8) single-photon avalanche diode (SPAD) pixel array, an edge-sensitive decision tree, a shared time-to-digital converter (TDC), 21-bit per-pixel memory, and in-locus data processing. Each module operates autonomously, by internal data acquisition, management, and storage, being periodically read out by an external access. The prototype was fabricated in a TSMC 3-D-stacked 45/65-nm CMOS technology, featuring backside illumination (BSI) SPAD detectors on the top tier, and readout circuit on the bottom tier. The sensor was characterized by single-point measurements, in two different modes of resolution and range. In low-resolution mode, a maximum of 300-m and 80-cm accuracy was recorded; on the other hand, in high-resolution mode, the maximum range and accuracy were 150 m and 7 cm, respectively. The module was also used in a flexible scanning light detection and ranging (LiDAR) system, where a 256 $\times $ 256 depth map, with millimeter precision, was obtained. A laser signature based on pulse-position modulation (PPM) is also proposed, achieving a maximum of 28-dB interference reduction.

We present the world's first backside-illuminated (BSI) single-photon avalanche diode (SPAD) based on standard silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology. This SPAD achieves a good dark count rate (DCR) after backside etching, comparable to DCRs of BSI SPADs fabricated on bulk wafers. Unlike bulk-wafer-based BSI SPADs, which typically suffer from poor violet and blue sensitivity, the proposed BSI SPAD features increased near-ultraviolet sensitivity as well as significant sensitivity in the violet and blue spectral ranges, thanks to the ultrathin-body SOI. To the best of our knowledge, this is the best result ever reported for any BSI SPAD in the standard CMOS technology. In addition, it also shows high sensitivity at long wavelengths thanks to the interface between silicon and silicon-dioxide layers. Therefore, it achieves a photon detection probability over 26% at 500 nm and 10% in the 400-875 nm wavelength range at 3 V excess bias voltage. The timing jitter is 119 ps full width at half maximum at the same operation condition at 637 nm wavelength. For the proposed BSI SPAD, the buried oxide layer in SOI wafers is used as an etching stop during the wafer backside-etching process, and therefore it ensures the excellent performance uniformity in large arrays.

한국은 노인 인구 비율이 14%를 넘긴 고령사회로 접어들면서 성공적 노화에 대한 관심이 높아지고 있다. 본 연구는 설문조사 방식으로 생활체육의 임파워먼트 제고 효과에 대해 분석하고 인구학적 요인뿐만 아니라, 사회경제적 요인이 생활체육과 결부하여 임파워먼트 제고에 어떻게 작용하는지에 대해서 분석하였다. 임파워먼트는 성공적 노화의 중요한 단면 중 하나라는 사실이 검증되고 있다. 18개 항목으로 요인분석을 실시한 결과 생활체육 활동을 하는 노년층의 심리적 임파워먼트 하위요인은 의미성, 자신감/자기결정력, 영향력, 그리고 집단 임파워먼트라는 사실이 나타났다. 한국 노인을 대상의 선행연구에서처럼 자신감과 자기결정력은 두 개의 요인으로 나누어지지 않았다. 네 개의 하위요인을 종속변수로 하고 실시한 다중회귀분석 결과 생활체육은 임파워먼트의 하위요인 중에서 의미성, 자신감/자기결정력. 그리고 집단 임파워먼트 제고에 긍정적 영향을 미치는 것으로 나타났다. 인구학적 변수 중 연령은 자신감/자기결정력에는 부정적 영향을 미치지만 영향력에는 긍정적 영향을 미치는 것으로 나타났다. 그러나 노화태도는 임파워먼트의 어떤 요인과도 통계적으로 유의미한 관계가 없었다. 생활체육 활동을 통하여 노인 임파워먼트는 제고될 수 있으며 노인들의 주체적인 삶에 긍정적으로 작용할 수 있다는 연구 결과는 성공적인 노화를 위한 정책개발에 활용할 수 있을 것으로 판단된다.

An efficient photo-annealing approach for high-performance solution-processed metal-oxide thin film transistors (TFTs) was demonstrated by using programmable pulse operation of xenon flash lamp. The flash lamp annealing (FLA) process could offer not only low-temperature (≈100° C) processing but also ultra-fast annealing speed of the order of seconds under air ambient conditions. Solution-processed amorphous indium-gallium-zinc-oxide (α-IGZO) TFTs implemented by the FLA process typically exhibited much improved electrical performance such as saturation mobility of >10.8 cm2V−11s−1, ION/IOPP of >108, and subthreshold slope of as steep as 0.24 V/dec. X-ray photoelectron spectroscopy analysis of a-IGZO films indicates that the FLA can provide sufficient activation energy for rapid formation of solid a-IGZO bonds within 30 s. The high-quality metal-oxide films achieved by an atmospheric and low temperature FLA method may represent a significant advance for scalable fabrication of flexible and printed metal-oxide electronics.

3D vision is an increasingly important feature in many applications of consumer, automotive, industrial, and medical imaging. Long range, high depth resolution, high spatial resolution, and high frame rates, are often conflicting requirements and difficult to be simultaneously achieved, especially in extreme ambient light conditions. In order to address range and depth resolution, direct time-of-flight has emerged as a powerful technique to perform light detection and ranging (LiDAR), thanks to advances in low-jitter optical detectors, such as single-photon avalanche diodes (SPADs), and accurate time-to-digital converters (TDCs) [1]–[5]. High spatial resolution can be achieved using scanning, at a cost of system complexity and somewhat lower frame rates [1], [3], while FLASH sensors [2], 4, [5] offer an alternative for both high frame rates and large pixel counts, but at limited ambient light conditions, due to typically long exposure times.

This paper presents the effect of shallow trench isolation (STI) on the dark count rate (DCR) and after-pulsing probability (APP) of deep-junction-based single-photon avalanche diodes (SPADs). Two different SPADs were fabricated in 110 nm CMOS image sensor technology, one with STI and the other without STI between its anode and cathode. With TCAD simulations and measurements, we have clearly demonstrated that the SPAD without STI enables a dramatic decrease in DCR by more than three orders of magnitude without suffering from the lateral leakage current between the anode and cathode. By excluding the STI from the device, the proposed SPAD also achieves a negligible APP while the SPAD with STI shows a very high APP of 92%. Thanks to the low-noise performance, the proposed SPAD becomes operable with higher excess bias voltage so that it achieves good photon detection probability, 58.3% at 500 nm and 3% at 940 nm, and timing jitter, 71 ps full width at half maximum at 670 nm, when the reverse bias voltage is 17 V.

We present a frontside-illuminated (FSI) multichannel digital silicon photomultiplier (MD-SiPM) fabricated in 0.18 µm/0.18 µm 3D-stacked CMOS technology. The top tier is dedicated to the FSI photodetectors, while the bottom tier comprises timestamping, processing, and communication electronics. The MD-SiPM is segmented in two arrays of 8×8 clusters of 64 single-photon avalanche diode (SPAD) pixels each. A dedicated time-to-digital converter (TDC) is included within each cluster. The pixel pitch is 50 µm, the fill factor 67%, and the peak PDE 35% at 500 nm. The TDC is triggered by the first firing SPAD, and its identification code or address is propagated and stored by a winner-take-all architecture. The 128+1 TDCs, which are based on a multi-path gated ring oscillator, exhibit an LSB of 8 ps and a single-shot resolution of 50 ps (RMS) as determined through initial measurements on an independent structure. The power consumption per TDC is below 1.8 mW. The data is validated and read out from the clusters through an on-chip scheduling controller, while a random-access architecture enables access of each cluster individually. Preliminary characterization demonstrates the suitability of the system for the target application.

With the Growth of Big Data technology, Artificial Intelligence technology, especially Deep Learning, is growing rapidly. In Deep Learning technology that like Convolutional Neural Network (CNN), collecting and training a sizeable befitting training data has a significant impact on technology maturity and completeness. But it is difficult for a person to collect a sizeable training data directly, and there are some problems in collecting it automatically with an ordinary web image crawler. For example, the name of a car is often obtained from a specific place name. When these keywords are crawled, the crawler retrieves only the text metadata of the image and gets the image. As a result, the crawler collects all images of different but has the same text. Also, even if the image of the car has been collected, only some of the car's interior or only a portion of the data that is not suitable for learning is also collected. In this paper, we present a method to classify and collect only data that is suitable for learning among crawled images using deep learning networks. Also, we offer a method to automatically generate training data by detecting objects and making object coordinates necessary for CNN learning at the same time.

The goal of this paper is to introduce single-photon avalanche diodes (SPADs) in CMOS technology, which are getting a lot of attention especially from the industry to realize low- cost and compact solid-state LiDAR sensors.

This paper discusses design optimization for silicon avalanche photodetectors (APDs) fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology in order to achieve the highest possible performance. Such factors as PN junctions, guard ring structures, active areas, and back-end structures are considered for the optimization. CMOS-APDs reflecting varying aspects of these factors are fabricated and their performances are characterized. In addition, their characteristics are analyzed with technology computer-aided-design simulations and equivalent circuit models. From these investigations, dominant factors that influence the CMOS-APD performance are identified. Furthermore, three different techniques enabling further performance improvements of CMOS-APDs are investigated, which are spatial-modulation, carrier-acceleration, and multijunction techniques. The state-of-the-art CMOS-APDs’ structures and performances are presented and compared, and the best optimized CMOS-APD is proposed. These results should be extremely useful for realizing optimal silicon APDs in standard CMOS technology for various applications.

We report a skin-like full-band on-chip photodetector enabled by two-dimensionally pixelized chalcometallate ligand quantum dots., Direct full-color photodetectors without sophisticated color filters and interferometric optics have attracted considerable attention for widespread applications. However, difficulties of combining various multispectral semiconductors and improving photon transfer efficiency for high-performance optoelectronic devices have impeded the translation of these platforms into practical realization. Here, we report a low-temperature (4.2 × 1017 Jones) and photoresponsivity (>8.3 × 103 A W−1) in a broad range of wavelengths (365 to 1310 nm). On the basis of these technologies, a wavelength discriminable phototransistor circuit array (>600 phototransistors) was implemented on a skin-like soft platform, which is expected to be a versatile and scalable approach for wide spectral image sensors and human-oriented biological devices.

The development of lampreys has fascinated evolutionary developmental (evo-devo) biologists for a long time. Lampreys, as one of the two surviving members of an ancient group of jawless vertebrates, have long been recognized as key for understanding vertebrate evolution due to their basal position in vertebrate phylogeny. While classical descriptions of lamprey development have uncovered many similarities in development among the few lamprey species that have been studied, these studies, together with modern techniques, have provided key insights for understanding how developmental changes have been important for vertebrate evolution. In recent years, the sea lamprey Petromyzon marinus has moved to the forefront of studies on lamprey development due to its invasion into the Great Lakes, and the critical need to understand its biology for management purposes. The sea lamprey genome has also been published and these two developments, taken together, facilitate the use of lampreys in evo-devo investigations. Here we provide a current overview of contributions of lamprey developmental studies for understanding vertebrate evolution, a summary of modern molecular and genetic tools and methods that have been applied in lamprey evo-devo research. Finally, we provide information to facilitate setting up the lamprey as a model organism in a modern research laboratory setting.

— For on-chip data communication with galvanic isolation, a monolithically integrated optocoupler is strongly desired. For this purpose, silicon (Si) avalanche mode LEDs (AMLEDs) offer a great potential. However such AMLEDs have a relatively low internal quantum efficiency (IQE) and high power consumption. For the first time, in this work, data communication in a monolithically integrated optocoupler is experimentally demonstrated. The novelty of this work is the use of highly sensitive single-photon avalanche diodes (SPADs) for photo-detection to compensate for the low IQE of AMLEDs. We investigated our optocoupler realized in a standard 140 nm CMOS SOI technology, without postprocessing, for various LED designs and points of operation. The power consumption of the AMLEDs is minimized through a novel AMLED design and employment of a low power LED driver circuit. The advantages of AMLEDs over forward biased Si LEDs are also demonstrated. For the best AMLED design, the achievable data rate is few Mbps and the energy consumption a few nJ/bit. The active area of the proposed systems is < 0.01 mm2.

This letter reports on the first silicon avalanche photodetectors (APDs) with over 10-GHz bandwidth. Three types of APDs based on P+/N-well junction are realized in standard complementary metal–oxide–semiconductor (CMOS) technology. For bandwidth improvement, the CMOS-compatible APDs (CMOS-APDs) are designed to be smaller active area, and a spatially-modulated avalanche photodetector (SM-APD) is also proposed in order to further reduce the bandwidth limiting factor of the CMOS-APDs. Current–voltage characteristics, responsivities, and photodetection frequency responses of the three APDs are measured and compared, and the photodetection bandwidth characteristics are analyzed with an equivalent circuit model to identify the origin of the bandwidth improvement. The proposed small-area CMOS-APD provides 10-GHz bandwidth with high responsivity, and the SM-APD achieves 12-GHz bandwidth, which is the largest bandwidth ever reported for silicon photodetectors in standard CMOS technology.

We investigate the effects of parasitic resistance on the performance of silicon avalanche photodetectors (APDs) fabricated in the standard complementary metal–oxide–semiconductor (CMOS) technology. Two types of CMOS-APDs based on the P+/N-well junction having two different parasitic resistances are realized, and their current–voltage characteristics, responsivities, avalanche gains, photodetection frequency responses, and electrical reflection coefficients are measured and compared. In addition, the effect of parasitic resistance on the photodetection bandwidth is analyzed with an equivalent circuit model. It is clearly demonstrated that the parasitic resistance has great effects on the gain and photodetection bandwidth of CMOS-APDs.