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4 × 288 heteroepitaxial mercury–cadmium telluride (MCT) linear arrays for long wavelength infrared (LWIR) applications with 28 × 25 micron diodes and charge coupled devices (CCD) silicon readouts were designed, manufactured and tested. MCT heteroepitaxial layers were grown by MBE technology on (0 1 3) GaAs substrates with CdZnTe buffer layers and had cutoff wavelength λ co ≈11.8±0.15 μm at T =78 K. To decrease the surface influence of carrier recombination processes the compositionally dependent layers with increase of Cd content both toward the surface and HgCdTe/CdZnTe boundary interface were grown. Silicon readouts with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure, to qualify readout integrated circuits on wafer level at T =300 K, was worked out. The silicon readouts for 4 × 288 arrays, with skimming and partitioning functions included were manufactured by n-channel MOS technology with buried or surface channel CCD register. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4 × 288 MCT n–p-junctions, the detectivity for several tested 4 × 288 arrays was within D λ ∗ ≅9×10 10 –1.8×10 11 cm Hz 1/2 /W for background temperature T b =295 K.

x4×288 heteroepitaxial mercury-cadmium telluride (MCT) linear arrays for long wavelength infrared (LWIR) applications with 28×25 micron diodes and charge coupled devices (CCD) silicon readouts were designed, manufactured and tested. MCT heteroepitaxial layers were grown by MBE technology on (013) GaAs substrates with CdZnTe buffer layers and have cutoff wavelength λco ≈ 11.8 μm at T = 78 K. To decrease the surface influence of the carriers recombination processes the layers with composition changes and its increase both toward the surface and HgCdTe/CdZnTe boundary were grown. Silicon read-outs with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure to qualify read-out integrated circuits (ROICs) on wafer level at T = 300 K was worked out. The silicon read-outs for 4×288 arrays, with skimming and partitioning functions included were manufactured by n -channel MOS technology with buried or surface channel CCD register. Designed CCD readouts are driven with four- or two-phase clock pulses. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4×288 MCT n-p-junctions, the detectivity was about (formula available in paper) for background temperature Tb = 295 K.© (2003) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.