Search

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( $V_{\mathrm{ bs}}$ ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive $V_{\mathrm{ bs}}$ due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate.

We present and thoroughly compare band-structures computed with density functional theory, tight-binding, k · p and non-parabolic effective mass models. Parameter sets for the non-parabolic Γ , the L and X valleys and intervalley bandgaps are extracted for bulk InAs, GaAs and InGaAs. We then consider quantum-wells with thickness ranging from 3 nm to 10 nm and the bandgap dependence on film thickness is compared with experiments for In 0.53 Ga 0.47 As quantum-wells. The impact of the band-structure on the drain current of nanoscale MOSFETs is simulated with ballistic transport models, the results provide a rigorous assessment of III–V semiconductor band structure calculation methods and calibrated band parameters for device simulations.

We present a tri-gate In0.53Ga0.47As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture. The fabricated devices feature a 20-nm-thick n-In0.53Ga0.47As channel doped to 1018/cm3 obtained by metal organic chemical vapor phase deposition and direct wafer bonding along with a 3.5-nm-thick Al2O3 gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The PE-ALD Al2O3 presents a bandgap of 7.0 eV, a k-value of 8.1 and a breakdown field of 8–10.5 MV/cm. A post-fabrication H2/Ar anneal applied to the PE-ALD Al2O3/In0.53Ga0.47As-OI gate stack yielded a low density of interface traps (Dit) of 7 × 1011/cm2 eV at Ec − E = −0.1 eV along with lower border trap density values than recently reported PE-ALD bi-layer Al2O3/HfO2 and thermal ALD HfO2 gate stacks deposited on In0.53Ga0.47As. The H2/Ar anneal also improved the subthreshold performance of the tri-gate InGaAs-OI JLFETs. After H2/Ar anneal, the long-channel (10 μm) device featured a threshold voltage (VT) of 0.25 V, a subthreshold swing (SS) of 88 mV/dec and a drain-induced barrier lowering (DIBL) of 65 mV/V, while the short-channel (160 nm) device exhibited a VT of 0.1 V, a SS of 127 mV/dec and a DIBL of 218 mV/V. Overall, the tri-gate InGaAs-OI JLFETs showed the best compromise in terms of VT, SS and DIBL compared to the other III–V JLFET architectures reported to date. However, a 15× increase in access resistance was observed after H2/Ar anneal, significantly degrading the maximum drain current of the tri-gate InGaAs-OI JLFETs.

1. Introduction As Si-CMOS scaling is becoming increasingly challenging, III-V compound semiconductors such as InxGa1-xAs (x≥0.53) (InGaAs) are receiving an increasing interest as channel material for nFET [1,2]. Together with SiGe as a pFET channel, they are considered as potential candidates to replace silicon for low power, high performance CMOS thanks to their better transport properties. A prerequisite in view of integration at VLSI scale is the formation of high quality III-V heterostructures on a silicon substrate to enable production on large size wafers. III-V integration on Si by direct wafer bonding is considered as one of the possible paths towards this objective [3]. Our rationale is that (1) InGaAs-on-insulator can be fabricated with the appropriate critical dimensions and thermal stability, (2) source wafers can be fabricated on large diameter wafers with acceptable defect densities and (3) hybrid substrates can be used to fabricate simple CMOS circuits. 2. InGaAs-on-Insulator A possible fabrication path for InGaAs-On-Insulator substrate is summarized. For demonstration purposes, the source substrate can simply be etched. A manufacturable process will however rely on the H-induced thermal splitting, as demonstrated in [3]. For thin layers as required for advanced CMOS, the thickness of InGaAs-o-I is below the critical value determined by the thermal strain up to 600°C. In addition, the interface energy at the Al2O3-Si bonding interface is almost 1 J/m2, larger than the one determined for SiO2-Si bonding in SOI wafers [4]. Such structures can therefore undergo high temperature processes such as the regrowth of highly doped InGaAs source and drain. The thermal stability is illustrated by showing that the regrowth of InGaAs do not degrade the structural quality of the underlying ultra-thin InGaAs-o-I. Functional self-aligned devices have been processed down to short gate length Lg=24nm, demonstrating the stability of such structures [5]. 2. Large diameter source wafer For VLSI integration, the bonding flow must be available for large diameters. As no InP substrate is available above 4”, the only possibility is to grow a virtual donor wafer onto a large diameter silicon substrate. Low defect density as well as very low roughness is required. In our internal work, GaAs deposition is performed by MBE on 200mm Ge/Si (001) substrate 6° off-cut, and subsequent pseudomorphic InxAl1-xAs grading buffer (x~ 0-0.65) allows reaching InP lattice-matching conditions. The formation of a thin InGaAs active layer completes the heterostructure that is compatible with the direct wafer bonding process. The best rms/TDD values reported so far are for GaAs 1nm/low-107cm-2 , and for InGaAs 2nm/mid-108cm-2. , close to the best value reported so far for Aspect Ratio Trapping methods. Excellent device metrics have been obtained on such heterostructures, supporting the idea that they can be used as donor wafers. 3. Hybrid circuits Based on the previous results, the co-integration of fully depleted InGaAs and SiGe MOSFETs can be envisioned. Starting from an 8 nm thick ETSGOI wafer, a 6 nm thick InGaAs layer can be transferred as in [6]. Because of the low temperature used during wafer bonding, and due to the presence of the BOX, cross-diffusion between InGaAs and SiGe is inhibited. The n- and p- active regions are defined based on mesa definition in the InGaAs and SiGe layer. The rest of the process follows an ETSOI-like front-end where n- and p-FETs are processed simultaneously. Such an hybrid structure is shown, for which a simplified process has been utilized, including a common gate stack and metal source drain instead of raised source/drain. The device characteristics have been extensively reported in [6], and a typical inverter transfer characteristic has been obtained, leading to the first demonstration of hybrid CMOS circuits based on high mobility channels. [1] J. Lin, D. A. Antoniadis and J. A. Del Alamo, IEDM Tech. Dig. (2012) [2] M. Radosavljevic, G. Dewey, D. Basu, J. Boardman, B. Chu-Kung, J. M. Fastenau, S. Kabehie, J. Kavalieros, V. Le, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, N. Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, U. Shah, H. W. Then and Robert Chau, IEDM Tech. Dig. (2011) [3] L. Czornomaz, N. Daix, D. Caimi, M, Sousa, R. Erni, M. D. Rossell, M. El-Kazzi, C. Rossel, C. Marchiori, E. Uccelli, M. Richter, H. Siegwart and J. Fompeyrine, IEDM Tech. Dig. (2012) [4] N. Daix, L. Czornomaz, D. Caimi, C. Rossel, M. Sousa and J. Fompeyrine, S3S conference 2013 [5] L. Czornomaz, et al., Proc. ESSDERC 2013 [6] L. Czornomaz, et al., IEDM Tech Digest (2013)

We have investigated the strain effects on the effective channel mobility of InGaAs pseudo (Ψ) n-MOSFETs by means of mechanical beam bending technique. For this goal, III–V heterostructures were grown on InP and transferred onto Si by direct wafer bonding. We show that an increase in electron mobility of up to 70% can be achieved under tensile strain. Simulations of InGaAs band-structure parameters under strain suggest that in the present case mobility enhancement is due to an increase of the sheet carrier density rather than to a decrease of the effective mass.

We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique (DWB) as well as a replacement gate process for self-aligned fully depleted InGaAs MOSFETs. These combined achievements highlight the viability of our approach for the VLSI integration of InGaAs at advanced nodes. Short channel replacement gate (RMG) and Gate-first (GF) FETs are reported for the first time using InGaAs-OI wafers with a 120nm contact-to-contact pitch. Record I ON (118 µA/µm) at fixed operating voltage of 0.5V for InGaAs devices on Si is achieved on 50-nm-Lg RMG FinFETs. Both schemes feature highly scaled fins (down to 15 nm). Compared to a GF integration flow, RMG devices exhibit better I on and DIBL characteristics. We also demonstrate FETs with 70 nm contacts and 120 nm pitch achieving high-I ON .

Display Omitted 50nm InGaAs on insulator layers successfully transferred using wafer bonding.We fabricated semiconductor/insulator/semiconductor capacitor structures.CV characteristics were measured and compared to simulated small ac signal CVs.This approach is suitable for the study of the insulator/InGaAs bottom interface. The electrical properties of Au/Ni/In0.53Ga0.47As/Al2O3/SiO2/Si structures were investigated using capacitance voltage (C-V) analysis. The properties of the InGaAs on insulator structures were analysed by comparing the measured and the theoretical C-Vs obtained using a physics based simulation of this structure. The results show that the measured data obtained on both n-type and p-type silicon match very well the simulated data. This work also shows that this approach allows the characterisation of charges in the buried oxide as well as interface states at the bottom InGaAs/Al2O3 interface.

A tri-gate In 0.53 Ga 0.47 As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture is demonstrated. The devices feature a 20-nm-thick n-In 0.53 Ga 0.47 As channel doped to 1018 /cm3 obtained by direct wafer bonding and a 3.5-nm-thick A1 2 O 3 gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The impact of the fin width (W fin ) and gate length (L g ) scaling at fixed channel doping (N d ) and equivalent oxide thickness (EOT) on the device performance is discussed and benchmarked.

We compare band-structure calculations obtained with modeling approaches hierarchically spanning from density functional theory to tight-binding, k·p and non-parabolic effective mass descriptions. We consider III-V quantum-wells with thickness ranging from 3nm to 10nm. Comparison with experiments for unstrained and strained InGaAs quantum-wells is also reported.

We report a self-aligned InGaAs Quantum-Well MOSFET (QW-MOSFET) on III-V-O-I substrate fabricated through a tight-pitch process. The ultra-thin body (UTB) III-V-O-I layer structure was fabricated on Si through a direct bonding technique. The III-V MOSFETs, with a self-aligned gate and metal contacts, were fabricated by a gate-last method. For the first time, we demonstrate adjacent devices with contact metal spacing of 150 nm. The fabrication features CMOS compatibility with a wet-etch free, lift-off free and Au-free process in the front end. Transport and short-channel effects (SCE) are studied as a function of back bias. Excellent SCE control is obtained with DIBL and subthreshold swing benchmarked against state-of-the-art III-V-O-I data. The reported technology provides a new path to integrate III-V front-end devices for future high density circuit applications.

As Si-CMOS scaling has become increasingly challenging, III-V compound semiconductors such as In x Ga 1-x As (x≥0.53) (InGaAs) are receiving much interest as channel material for nFET [1,2]. Together with SiGe as a pFET channel, they are considered as potential candidates to replace silicon for low power, high performance CMOS thanks to their better transport properties. A prerequisite in view of integration at VLSI scale is the formation of high quality III-V heterostructures on a silicon substrate to enable production on large size wafers.

Direct wafer bonding can be a vehicle for the dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs. Like for SiGe, direct wafer bonding enable the fabrication of fully depleted transistors having superior electrostatic control over the channel. Hybrid substrates can be also fabricated by direct wafer bonding with stacked ultra-thin high-mobility layers. A process flow allows fabricating n- and p-channel field effect transistors with ultra-thin body and BOX on the same wafer. Working CMOS inverters are obtained using a common front-end.

We demonstrate for the first time a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI). We first show that such hybrid substrates can be fabricated by direct wafer bonding with stacked high-mobility layers thinner than 8nm. A process flow is presented that allows us to fabricate n- and p-channel field effect transistors with ultra-thin body and BOX (UTBB-FET) on the same wafer. Gate lengths down to 40nm produced at sub-μm gate-pitch are achieved. Working CMOS inverters are obtained using a common front-end which confirms the viability of this integration scheme for hybrid high-mobility dual-channel CMOS. We also highlight that back-biasing technique for Vt tuning can still be used despite the dualchannel structure, as implemented in standard ETSOI circuits.

Ultra-thin-body on buried oxide (UTBB) InGaAs are promising layers for the next generation of transistors. One way to fabricate InGaAs layer on Si or SiGe substrates is the direct wafer bonding technique with ion implantation and thermal splitting. We have investigated the bonding energy of two possible candidates for the buried oxide (BOX), Al2O3 and SiO2, between room temperature and 450°C. Then we have compared the properties of InAlAs, InP and InGaAs buffers for the implantation and splitting processes.

In this work, we show for the first time that VLSI-like gate-first self-aligned InGaAs MOSFETs on insulator on Si featuring raised source/drain (SID) can be fabricated at 300 nm pitch with gate lengths down to 24 nm. This is made possible thanks to the excellent thermal stability of ultra-thin-body and BOX InGaAs on insulator which can be used as a crystalline seed for III-V regrowth. The devices exhibit an excellent electrostatic integrity down to L G = 34 nm, comparable to the best reported tri-gate devices. We compare experimental device data to electrostatic simulations for bulk/on-insulator/tri-gate structures and extrapolate their ultimate scalability to very short L G .

Strain effects on the effective channel mobility of InGaAs pseudo (Ψ) n-MOSFETs are investigated using the mechanical beam bending technique. For this purpose III-V heterostructures grown on InP are transferred to Si by direct wafer bonding. An electron mobility increase up to 70% can be achieved under tensile strain. By comparison with simulations of InGaAs band structure parameters under strain, we suggest that this mobility enhancement is due to an increase of the sheet carrier density rather than to a decrease of the effective mass.

In this work we demonstrate for the first time that the excellent thermal stability of ultra-thin body (UTB) III-V heterostructures on silicon provides a path for the cointegration of self-aligned In 0.53 Ga 0.47 As MOSFETs with silicon. We first demonstrate that the transfer of high-quality InGaAs / InAlAs heterostructures (t ch < 10 nm) can be achieved by direct wafer bonding and hydrogen-induced thermal splitting, and that the donor wafer can be recycled for a cost-effective process. The thermal stability of the bonded layer enables to integrate UTB III-V MOSFETs at 500 nm pitch using a gate-first flow featuring raised source/drain (S/D) grown at 600oC. The expected benefit of an UTB structure is benchmarked by comparing sub-threshold slope (SS) and drain-induced-barrier-lowering (DIBL) against state-of-the-art III-V-o-I or Tri-Gate FET data.

International audience; We have performed systematic measurements of the splitting kinetics induced by H-only and He + H sequential ion implantation into relaxed Si$_{0.8}$Ge$_{0.2}$ layers and compared them with the data obtained in Si. For H-only implants, Si splits faster than Si$_{0.8}$Ge$_{0.2}$ Sequential ion implantation leads to faster splitting kinetics than H-only in both materials and is faster in Si$_{0.8}$Ge$_{0.2}$ than in Si. We have performed secondary ion mass spectrometry, Rutherford backscattering spectroscopy in channeling mode, and transmission electron microscopy analyses to elucidate the physical mechanisms involved in these splitting phenomena. The data are discussed in the framework of a simple phenomenological model in which vacancies play an important role.