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We have fabricated and demonstrated a new device called the Vertical Replacement-Gate (VRG) MOSFET. This is the first MOSFET ever built that combines (1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and (2) a high-quality gate oxide grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes a self-aligned S/D formed by solid source diffusion (SSD) and small parasitic overlap, junction, and S/D capacitances. The drive current per /spl mu/m of coded width is significantly higher than that of advanced planar MOSFETs because each rectangular device pillar (with a thickness of minimum lithographic dimension) contains two MOSFETs driving in parallel. All of this is achieved using current manufacturing methods, materials, and tools, and competitive devices with 50-nm gate lengths (L/sub G/) have been demonstrated without advanced lithography.

A number of groups have reported that the stress-induced leakage current (SILC) follows a power law dependence on the stress time. In this study, we observed that the power-law behaviour is only an approximation of the fast rising part of a more complex behaviour. SILC rises during the initial stress stage and saturates after a long stress time. Based on the trap-assisted tunneling (TAT) model, we show that the stress time dependence of SILC is better described as the depletion of multi-precursors of traps. Although the new model involves many fitting parameters, we show that the fitting results are consistent with the physical interpretation of these parameters. To further support the physical interpretation, we examined these parameters with annealing experiments.

A 1296-port MEMS transparent optical crossconnect with 5.1dB/spl plusmn/1.1dB insertion loss at 1550 nm is reported. Measured worst-case optical crosstalk in a fabric was n38 dB and nominal switching rise/fall times were 5 ms. A 2.07 petabit/s switch capacity was verified upon cross-connecting a forty-channel by 40 Gb/s DWDM data stream through a prototype fabric.

We have investigated a new class of high K gate dielectric materials, Si-doped aluminates. These dielectrics, with TiN gates, can withstand high temperature CMOS processing and therefore do not require replacement gate technology. In this paper we focus on Si-doped zirconium aluminate (Zr-Al-Si-O), with K/spl sim/20. With the TiN gate stack subjected to the standard CMOS thermal budget, we have scaled this dielectric to t/sub eq//spl sim/1.2 nm with leakage current 15) may be viable alternate gate dielectrics.

We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year, these devices show promise as a successor to planar MOSFETs for highly-scaled ULSI. Our pMOSFETs retain the key features of the nMOSFETs and add channel doping by ion implantation and raised source/drain extensions (SDEs). We have significantly improved the core VRG process to provide high-performance devices with gate lengths of 100 nm and below. Since both sides of the device pillar drive in parallel, the drive current per /spl mu/m of coded width can far exceed that of planar MOSFETs. Our 100 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ drive 615 /spl mu/A//spl mu/m at 1.5 V with I/sub OFF/=8 nA//spl mu/m-80% more drive than specified in the 1999 ITRS Roadmap at the same I/sub OFF/. We demonstrate 50 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ that approach the 1.0 V roadmap target of I/sub ON/=350 /spl mu/A//spl mu/m at I/sub OFF/=20 nA//spl mu/m without the need for a hyperthin (

A one-mask metal-insulator-metal (MIM) capacitor using damascene Ca as the bottom electrode has been developed. Using a PECVD SiN as both the capacitor dielectric and the diffusion barrier for Cu we have demonstrated for the first time, the achieving of low leakage, high linearity MIM capacitors directly on Cu. The leakage and breakdown characteristics of the MIM capacitor depend strongly on both the surface conditions of the damascened Cu and on the PECVD SiN. We found that multilayered SiN is superior than single layer SiN, and Cu CMP plays an important role. However, the inevitable dishing on large area capacitors during Cu CMP shows little impact on the electrical characteristics.

We have integrated HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics grown by atomic layer chemical vapor deposition (ALD) with poly-Si gate electrodes in the vertical replacement-gate (VRG) MOSFET geometry. These transistors are among the first reported with ALD HfO/sub 2/ gate dielectrics, and have HfO/sub 2/ target equivalent oxide thicknesses (tEOT's) down to 13 /spl Aring/. The poly-crystalline HfO/sub 2/ films in these VRG nMOSFETs exhibit extremely low gate leakage (GL) current densities of J/sub G/ /spl sim/ 10/sup -7/ A/cm/sup 2/ at V/sub G/-V/sub T,Long/ = 0.6 V for 15 /spl Aring/ tEOT devices. This indicates that amorphous gate dielectrics may not be necessary to meet GL requirements. HfO/sub 2/ devices with 50 nm gate length L/sub G/ exhibit drive currents [normalized by the coded width W/sub C/] of 490 /spl mu/A//spl mu/m for 1 V operation (overdrive V/sub GS/-V/sub T/ = 0.6 V) with good short-channel performance. These results demonstrate that ALD is compatible with the demanding VRG geometry, thereby illustrating that it should be well-suited to essentially any novel device structure built with Si-compatible materials.

A 72/spl times/72 wavelength-selective crossconnect switch, that is scalable to 1296/spl times/1296 with current technology, is presented. Silica-on-silicon wavelength multiplexers with integrated monitoring taps and a MEMS micromirror array were assembled in a hybrid 3D beam steering crossconnect having 20 dB insertion loss, 100 GHz channel spacing and 30 GHz passbands.