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4. Internet of Things in Agriculture

Author

Nacif, José Augusto M., de Oliveira, Herlon Schmeiske, Ferreira, Ricardo, Marçal de Queiroz, Daniel, editor, M. Valente, Domingos Sárvio, editor, de Assis de Carvalho Pinto, Francisco, editor, Borém, Aluízio, editor, and Schueller, John K., editor

Published
2022
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9. TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs

Author

Canesche, Michael, Menezes, Marcelo, Carvalho, Westerley, Sill Torres, Frank, Jamieson, Peter, Nacif, Jose Augusto, and Ferreira, Ricardo

Subjects
Very-large-scale integration, Scheduling, Computer science, 02 engineering and technology, Parallel computing, Computer Graphics and Computer-Aided Design, Simulated annealing, Graph, 020202 computer hardware & architecture, Scheduling (computing), Tree traversal, Hardware, 0202 electrical engineering, electronic engineering, information engineering, Graph (abstract data type), Computer architecture, Electrical and Electronic Engineering, Heuristics, Greedy algorithm, Field-programmable gate array, Integer programming, Software, Routing
Abstract

Coarse grain reconfigurable architectures (CGRAs) are an emerging hybrid computational architecture that has the parallel customization benefits of low-level logic devices, such as FPGAs and ASICs, while the relative coarseness of these architectures makes CGRAs easier to design for, which is more similar to the traditional processor. In the process of mapping designs to CGRAs, flexible, fast, and adaptive placement and routing (P&R) is fundamental in order to implement efficient run-time reconfigurable frameworks. It is well-known that P&R is an NP-complete problem, and thus, solutions rely on heuristics to achieve quality results with acceptable execution times. CGRA P&R has different constraints compared to traditional VLSI P&R, e.g., path latency balancing and modulo scheduling of loops. In this work, we propose a graph-based P&R approach that uses graph traversals to map designs to CGRAs. Additionally, we parallelize our approach with a graph-based greedy heuristic that executes on a GPU. We compare our proposed P&R approach with the CGRA-ME framework, which implements simulated annealing and integer linear programming placement algorithms. Our results show that this new approach can generate optimal mappings and improve the execution run-time up to several orders of magnitude. Furthermore, considering spatial mapping at the millisecond scale, our GPU approach is one order of magnitude faster compared to the state-of-the-art tool VPR.

Published
2021

10. On-Chip Property Verification Using Assertion Processors

Author

Nacif, José Augusto M., Coelho, Claudionor Nunes, Jr., Foster, Harry, de Paula, Flávio Miana, Mota, Edjard, Mota, Márcia Roberta Falcão, Fernandes, Antônio Otávio, Glesner, Manfred, editor, Reis, Ricardo, editor, Indrusiak, Leandro, editor, Mooney, Vincent, editor, and Eveking, Hans, editor

Published
2006
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44. Tracking hardware evolution

Author

Nacif, Jose Augusto, primary, Silva, Thiago S. F., additional, Vieira, Luiz Filipe M., additional, Vieira, Alex Borges, additional, Fernandes, Antonio O., additional, and Coelho, Claudionor, additional

Published
2011
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