120 results on '"Nakaharai, S."'
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2. Low-frequency noise in hBN/MoS2/hBN transistor at cryogenic temperatures toward low-noise cryo-CMOS device applications.
3. Effect of Parallel Magnetic Field on the Melting Transition in BSCCO
4. Ge wire MOSFETs fabricated by three-dimensional Ge condensation technique
5. Device structures and carrier transport properties of advanced CMOS using high mobility channels
6. Pinning of Vortices Nearly Parallel to the Superconducting Plane in κ-(ET)2Cu[N(CN)2]Br and κ-(ET)2Cu(NCS)2
7. High-performance (1 1 0)-surface strained-SOI MOSFETs
8. Sub-band structure engineering for advanced CMOS channels
9. Kinetics of epitaxial growth of Si and SiGe films on (1 1 0) Si substrates
10. Creeping of pinned vortex lines nearly parallel to the superconducting plane of Bi 2Sr 2CaCu 2O 8 in the irreversible region
11. Stitching of fluxoids parallel to the superconducting sheet in Bi 2Sr 2CaCu 2O 8+ δ
12. Gap Width Dependence of Transport through Quantum Point Contact in hBN/Graphene/hBN in the Quantum Hall Regime
13. Few-Layer ReS2 based Vertical p-n van der Waals Junction for Photosensing
14. Formation process of high-purity Ge-on-insulator layers by Ge-condensation technique
15. Wafer Scale Fabrication of Transistors using CVD-Grown Graphene and its Application to Inverter Circuit
16. Semiconducting properties of bilayer graphene modulated by an electric field for next-generation atomic-film electronics
17. Vortex lock-in phase diagram in κ-(ET) 2Cu[N(CN) 2]Br and κ-(ET) 2Cu(NCS) 2
18. Room Temperature On-Off Operation of Current in He Ion Irradiated Graphene Sheet
19. Gating Operation of Transport Current in Graphene Nanoribbon Fabricated by Helium Ion Microscope
20. Gate-Defined Graphene Quantum Point Contact in the Quantum Hall Regime
21. High Mobility sub-60nm Gate Length Germanium-On-Insulator Channel pMOSFETs with Metal Source/Drain and TaN MIPS Gate
22. Gate all around (GAA) strained-silicon-on-nothing (SSON) MOSFETs and evaluation of their strain by nano-beam diffraction (NBD)
23. Observation of Mobility Enhancement in Strained Si and SiGe Tri-Gate MOSFETs with Multi-Nanowire Channels Trimmed by Hydrogen Thermal Etching
24. Hole mobility enhancement of p-MOSFETs using global and local Ge-channel technologies
25. The generation of crystal defects in Ge-on-insulator (GOI) layers in the Ge-condensation process
26. Strained-SOI Technology for High-Speed CMOS Operation
27. Generation of Crystal Defects in Ge-on-Insulator (GOI) Layers in Ge-condensation Process
28. Formation of SGOI Structures with Low Dislocation Density by Two Step Oxidation and Condensation Method
29. Mobility-Enhanced CMOS Technologies Using Strained Si/SiGe/Ge Channels
30. High-Speed Source-Heterojunction-MOS-Transistor (SHOT) Utilizing High-Velocity Electron Injection
31. High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique
32. IEEE Transactions on Electron Devices
33. High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide Schottky source/drain
34. Kinetics of epitaxial growth of Si and SiGe films on (110) Si substrates
35. Gate-tunable control in graphene semiconductive channel.
36. Creeping of pinned vortex lines nearly parallel to the superconducting plane of Bi2Sr2CaCu2O8 in the irreversible region
37. Experimental Evidence of Low Dislocation Density of SiGe-on-Insulator Substrates Fabricated by Oxidizing SiGe/SOI Structures
38. High performance multi-gate pMOSFET using uniaxially-strained SGOI channels.
39. Device characterizations and physical models of strained-Si channel CMOS.
40. Scanning tunneling spectroscopy of (TMTSF)2ClO4 under magnetic fields at 0.3 K
41. Suppression of vortex pinning by field component parallel to the superconducting plane inBi2Sr2CaCu2O8
42. Vortex lock-in phase diagram in κ-(ET)2Cu[N(CN)2]Br and κ-(ET)2Cu(NCS)2
43. Creeping of pinned vortex lines nearly parallel to the superconducting plane of Bi<f>2</f>Sr<f>2</f>CaCu<f>2</f>O<f>8</f> in the irreversible region
44. High performance multi-gate pMOSFETs using uniaxially-strained SGOI channels
45. Gate-tunable control in graphene semiconductive channel
46. Strained-Si/SiGe-On-Insulator CMOS technology as a platform of device performance boosters
47. Strained-Si/SiGe-on-insulator wafers fabricated by Ge-condensation process
48. Strained SOI technology for high-performance, low-power CMOS applications
49. Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs
50. Physical mechanism for high hole mobility in [110]-surface strained- and unstrained-MOSFETs
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