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In this paper, a novel high-speed and energy-efficient 4–2 compressor cell is proposed using carbon nanotube field-effect transistors. The proposed compressor is realized efficiently based on NAND–NOR gates and multiplexers. To estimate the performance of the presented design, simulations are carried out using Synopsis HSPICE under different conditions. The results demonstrate the improvement of the proposed design compared to the best reference designs in terms of delay and energy consumption, by 20–26%, respectively. Also, the susceptibility of the proposed design against the process, voltage, temperature (PVT), and noise variations is examined. It is robust against PVT variations and high amplitude of noises compared with its counterpart. Further, embedding the proposed compressor in an 8 × 8-bit binary multiplier demonstrates that it has better speed and energy consumption with regard to its counterparts. [ABSTRACT FROM AUTHOR]

The review highlights possible research topics matching the experimental physics of matter with advances in electronics to improve the intelligent design and control of innovative smart materials. Specifically, following the European research guidelines of Key Enabling Technologies (KETs), I propose different topics suitable for project proposals and research, including advances in nanomaterials, nanocomposite materials, nanotechnology, and artificial intelligence (AI), with a focus on electronics implementation. The paper provides a new research framework addressing the study of AI driving electronic systems and design procedures to determine the physical properties of versatile materials and to control dynamically the material's "self-reaction" when applying external stimuli. The proposed research framework allows one to ideate new circuital solutions to be integrated in intelligent embedded systems formed of materials, algorithms and circuits. The challenge of the review is to bring together different research concepts and topics regarding innovative materials to provide a research direction for possible AI applications. The discussed research topics are classified as Technology Readiness Levels (TRL) 1 and 2. [ABSTRACT FROM AUTHOR]

As the core component of a nanopixel light-emitting display, the GaN-based nanoscale light-emitting diode (nLED) faces the problem of low electroluminescence efficiency resulting from the introduction of surface defects when its lateral size is reduced to the nanometer scale. Thus, reducing the surface defect density is an important direction in nLED-related research. This study, with the triboelectric nanogenerator-driven LED as its inspiration, reveals that surface defects have a positive impact on the performance of nLEDs driven by Maxwell's displacement current, and we call the related driving mode the noncarrier injection mode. Through finite element simulations, we studied the dynamic variations of the carrier concentration, the energy band, and the light emission rate to analyze the impact of the behavior of surface defect excitation on device performance. We found that surface defects can act as electron pumps under the combined effect of the reverse electric field and the built-in electric field and can generate carriers through surface defect excitation to increase the intensity of noncarrier injection luminescence, which is completely different from the traditional understanding of surface defects. In addition, we propose a tapered structure to further increase the light emission rate by regulating the behaviors of radiation recombination and surface defect excitation. The results of this work open a new perspective on the impacts of surface defects on nLEDs and provide significant information for additional applications of Maxwell's displacement current. [Display omitted] • Surface defects have a positive impact on the performance of MDC-nLEDs. • Surface defect excitation leads to carrier redistribution in MDC-nLEDs. • Surface defects acting as carrier pumps provide more carriers for light emission. • A tapered structure can improve output by regulating surface DE. [ABSTRACT FROM AUTHOR]

Density Functional Theory is utilized to scrutinize the electronic state of silicene and boron nano-onion which is a round compact mass formed by placing an N20, C20, and B20 fullerene within its parent atom fullerene B40. The NEGF is used to investigate the quantum transport at both equilibrium and non-equilibrium. Firstly the I-V curve for both silicene and boron-based devices is studied. From the results, it is concluded that boron-based devices are better than silicene. Therefore to get deeper insights into why boron-based devices are better transport properties of boron-based devices are suited. Later on, the transport mechanism is analyzed by computing the DOS, transmission and molecular spectra, HLG, I-V curve, electron densities, and differential conductance. When the Boron nano-onion is placed between the pair of Au electrodes. The calculated results are evaluated and a comparative study is done. From the results, it is deduced that the N20 variant nano-onion has reduced the HOMO-LUMO gap (HLG) and highest value of current in comparison to other devices. Thus by infusing a smaller fullerene of N20 inside the hollow cage of B40 fullerene the amplification of current and conductance can be observed in Boron-nano-onion in comparison to other devices. [ABSTRACT FROM AUTHOR]

Power consumption and especially leakage power are the main concerns of nano MOSFET technology. On the other hand, binary circuits face a huge number of interconnection wires, which results in power dissipation and area. Researchers introduced emerging nanodevices and multiple-valued logic (MVL) as two feasible solutions to overcome the challenges mentioned above. Carbon nanotube field-effect transistor (CNFET) is one of the emerging technologies that has some unique properties and advantages over MOSFET, such as adjusting the carbon nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility as P-FET and N-FET transistors. In this paper, we present a novel method for designing ternary logic circuits based on CNFETs. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state, which saves power while the circuits are not in use. Moreover, we designed a two-digit adder/ subtractor and a power-efficient ternary logic arithmetic logic unit (ALU) based on the proposed gates. The proposed ternary circuits are simulated using HSPICE via standard 32 nm CNFET technology. The simulation results indicate the designs' correct operation under different process, voltage, and temperature (PVT) variations. Also, simulation results show that the two-digit adder/ subtractor using our proposed gates has 12X and 5X lower power consumption and power-delay product (PDP), respectively, compared to previous designs. [ABSTRACT FROM AUTHOR]

Palm vein pattern recognition is one of the most promising and rapidly developing fields of study in biometrics, which makes it an important solution for identity security in biometrics-based user identification systems. Quantum-dot Cellular Automata (QCA) is a developing field of nanotechnology which facilitates the creation of nano-scale logical circuits. Irreversible technology has faced some difficulties, such as higher heat energy dissipation. Reversible logic is therefore essential where heat dissipation is almost insignificant. This article proposes QCA design of a reversible circuit for palm vein authentication utilizing the Feynman gate. Fully reversible Feynman gate is designed. Using this newly designed Feynman gate the palm vein authenticator circuit is designed. The theoretical values and the results of the simulation correspond to the reliability of the planned circuit. Circuit complexity and circuit cost are explored. Validation of authenticated users by the proposed authenticator explores its design accuracy as per theoretical values. Energy dissipation of the proposed designs shows that it remains within Lauderer's limit (0.06meV). This proves that the circuits designed are fully reversible in nature and dissipates very less amount of energy. Comparison with recent QCA state of the art architectures explores its characteristics.

In this paper, a new method for implementing all two-input logic gates on an identical single-stage structure is proposed. We have used unique characteristics of single-electron transistors, which have periodic output–input relation, to design the gates and implement all two-input logic gates (symmetric/non-symmetric, monotonic/non-monotonic) by a single-stage design including only one single-electron transistor. In conventional monotonic devices, such as BJTs and MOSFETs, implementing non-monotonic logic gates such as XOR and XNOR is impossible with a single-stage circuit and a multistage design is required which leads to more complexity, more chip area and higher power consumption. We present the proposed methodology at first, and then, the details of the designs are investigated. The results are obtained analytically using a new approach named two-potential and then confirmed by numerical methods. Furthermore, important characteristics of the proposed gates such as maximum operating temperature, speed of the gates and frequency limitations, power consumption (static and dynamic) and scaling to other technologies have been investigated. Finally, a general idea has been presented about the application of the introduced approach and gate structures in the field of logic circuit and system designing. [ABSTRACT FROM AUTHOR]

A combination of computational power provided by modern MOSFET-based devices with light assisted wideband communication at the nanoscale can bring electronic technologies to the next level. Obvious obstacles include a size mismatch between electronic and photonic components as well as a weak light–matter interaction typical for existing devices. Polariton modes can be used to overcome these difficulties at the fundamental level. Here, we review applications of such modes, related to the design and fabrication of electro–optical circuits. The emphasis is made on surface plasmon-polaritons which have already demonstrated their value in many fields of technology. Other possible quasiparticles as well as their hybridization with plasmons are discussed. A quasiparticle-based paradigm in electronics, developed at the microscopic level, can be used in future molecular electronics and quantum computing. [ABSTRACT FROM AUTHOR]

Abstract With the continuous increase in technological applications, the progress of new semiconductor materials continues to be a significant research field. In recent years, new materials such as molybdenum disulfide, has been researched as a substitute for graphene and silicon. The monolayer molybdenum disulfide (MoS 2), one of the promising 2D materials with a direct bandgap has high potential for applications in nano electronic devices, energy storage, photocatalysts, and chemical sensors. As such, this paper examines the present gas-sensing applications of MoS 2 and have been compared it with other nanomaterials. [ABSTRACT FROM AUTHOR]

In this paper, a low-power high-speed hybrid full adder cell is proposed, which is implemented based on two-input multi-threshold (Vt) XNOR circuit and transmission gate multiplexers. In order to implement this circuit, carbon nanotube field-effect transistors are utilized. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects of digital circuits: power, delay and power-delay product. The results are presented and confirm the superiority of the proposed cell with the previously reported one in different voltage levels, load conditions, temperatures and robustness in large structures and against process variations. [ABSTRACT FROM AUTHOR]

• An improved Feynman gate based on quantum-dot CA architecture is presented. • A comparison of the suggested gate to the quantum-dot CA-based designs is examined in terms of quantum cost. • The suggested quantum-dot CA-based Feynman gate is evaluated and validated using the truth table, assessing the circuit's functional efficacy. • A new reversible gate based on Feynman logic with a multi-layer construction is proposed that uses less space and a number of cells. Quantum-dot Cellular Automata (CA) is a suitable nanotechnology for replacing CMOS circuits. The majority, inverter, and reversible structures, are the primary building blocks in quantum-dot CA circuits. Since the reversible gates have recently attained great attention, this paper proposes a new design of a reversible building block based on the Feynman gate. The proposed quantum-dot CA-based Feynman gate is denser and has low delay than the existing circuits. This paper also tests the possible implementation of the proposed design in quantum-dot CA. The QCADesigner is employed to test the functionality of the proposed structure. The proposed efficient quantum-dot CA-based Feynman gate has only 36 cells in three-layer. It consumes 0.03 µ m2, which is the smallest among all previous designs. A quantum-cost comparison of the proposed reversible Feynman gate with conventional reversible gates demonstrates the cost-effectiveness of quantum-dot CA. The simulation result matched the truth table of the Feynman gate, indicating that the suggested quantum-dot CA architecture is functional. The proposed architecture can also be used for n -bit code converters as well. [ABSTRACT FROM AUTHOR]

A combination of computational power provided by modern MOSFET-based devices with light assisted wideband communication at the nanoscale can bring electronic technologies to the next level. Obvious obstacles include a size mismatch between electronic and photonic components as well as a weak light−matter interaction typical for existing devices. Polariton modes can be used to overcome these difficulties at the fundamental level. Here, we review applications of such modes, related to the design and fabrication of electro−optical circuits. The emphasis is made on surface plasmon-polaritons which have already demonstrated their value in many fields of technology. Other possible quasiparticles as well as their hybridization with plasmons are discussed. A quasiparticle-based paradigm in electronics, developed at the microscopic level, can be used in future molecular electronics and quantum computing.

Nanomaterials have been at the center of attraction for almost five decades as their contributions to different disciplines such as electronics, photonics and medicine are enormous. Various kinds of nanomaterials have been developed and are currently utilized in innumerable applications. Nevertheless, their simple realization and easy and efficient upscaling are topics under intense investigation. Innovative strategies have been adopted for nanomaterial synthesis and their usability. Here, we provide a brief overview on nanomaterials ranging from basic understanding of their structure-property relationship to advanced applications. This editorial covers various aspects about nanomaterials, which will be useful/attractive for beginners in the field of nanotechnology as well as for experts and for industrialists looking forward to exploit them for real world applications. [ABSTRACT FROM AUTHOR]

New active thermal-electronic device family is proposed. These devices operate by means of thermal (or hot electron) coupling between adjacent domains containing heating (input) and thermally sensitive (output) elements. The theoretical background, basic equations and comparison with the conventional electron devices are the main subject of this work. According to the theoretical assumptions the realization of the thermal-electronic device needs a very sensitive output element i.e. temperature sensor. Among others, the metal-insulator transition (MIT) based resistor fulfills this requirement. The MIT resistor itself has got thyristor-like I–V characteristics due to solely the high electric field, or Joule heating induced extremely strong step-like resistance drop at a given temperature. Using thermally coupled MIT and/or other resistors it is possible to build a special device, namely phonsistor (=phonon transistor). This device consists of only bulk type intrinsic domains, containing significantly fewer regions, junctions, depleted layers, surfaces and interfaces compared to conventional electron devices. Thus, these devices can be integrated together with each other and with conventional CMOS, forming, for example, thermal-electronic logic circuit (TELC) for the More-Than-Moore concept devices. [ABSTRACT FROM AUTHOR]

We describe the ion beam analysis activities at imec. Rutherford backscattering spectrometry and time of flight-energy (TOF-E) elastic recoil detection analysis are pursued to support the nano-electronics research and development. We outline the experimental set-up and we introduce a new data acquisition software platform. Finally, we illustrate the use of Rutherford backscattering spectrometry to map the thickness of a metallic thin film on a 300 mm Si wafer. [ABSTRACT FROM AUTHOR]

The rapid advancement of Quantum-dot cellular automata (QCA) technology has moved on to the effective methods for testing these circuits due to its insufficient reliability. The growing demand for fault tolerance and testability attracts more research on it. This paper targets, a novel parity preserving testable adder (t-Adder) in QCA which tackles the internal fault within the gate efficiently resulting a testable circuit. The fault patterns of t-Adder gate under cell deposition defects are investigated. The most striking characteristic of this logic is that it is completely testable for single as well as multiple stuck-at faults using only three test vectors. Also, the functionality and the defect tolerance of the proposed t-Adder under the Path Fault Secure (PFS) scheme are studied which ensures more reliability. A comprehensive power dissipation analysis, as well as structural analysis of the testable logic gates, is performed which signifies the dominance of t-Adder in low power consumption. Further, the programmable feature of t-Adder is utilized to implement an efficient ALU, realizing 10 important functions along with addition operation. The design of QCA layout, as well as functional verification of the proposed design, is performed using the QCADesigner and HDLQ tool respectively whereas the power dissipation is evaluated using QCAPro simulator. [ABSTRACT FROM AUTHOR]

Research in recent years has greatly advanced the understanding and capabilities of multi-beam interference (MBI). With this technology it is now possible to generate a wide range of one-, two-, and three-dimensional periodic optical-intensity distributions at the micro- and nano-scale over a large length/area/volume. These patterns may be used directly or recorded in photo-sensitive materials using multi-beam interference lithography (MBIL) to accomplish subwavelength patterning. Advances in MBI and MBIL and a very wide range of applications areas including nano-electronics, photonic crystals, metamaterials, subwavelength structures, optical trapping, and biomedical structures are reviewed and put into a unified perspective.

Traditional integrated electronics is based only on electric signal processing, thermal phenomena are considered as a parasitic (side) effect. However, the thermal state of a device may represent information too. Thermal-electronic devices and integrated circuits can be created using power dissipating and thermally sensitive elements, such as pn junctions, thermoelectric semiconductor devices, metal-insulator transition (MIT) or semiconductor-metal transition (SMT) resistors. We propose a new active thermal-electronic device, specifically, a phonsistor = phonon transistor, patent pending [1] . The basis of the way this device operates is the thermal or hot electron coupling between adjacent domains containing metal-insulator transition (MIT) material. [ABSTRACT FROM AUTHOR]

As the integrated circuit geometries shrink, it becomes important for the designers to take into consideration the reliability of the circuits. Different techniques can be used for reliability calculation or estimation. Some of these techniques are accurate but time-consuming while others are quick but not accurate . For example, using a set of mathematical equations for reliability estimation is very fast but not precise enough for large systems. Alternatively, Monte Carlo simulations are highly accurate, but very time-intensive. This work presents three different neural network models for estimating circuit reliability. The models provide better prediction accuracies than the mathematical technique. A reasonably large number of combinational circuits were simulated over a wide range of device reliabilities to collect the training data for the models. Multiple slices of an ISCAS-85 benchmark circuit were used to validate the models’ prediction results. [ABSTRACT FROM AUTHOR]

Zn-(FeO 2 ) 2 –graphene smart nano-composites were synthesized using a novel modified solvothermal synthesis with different percentages of graphene. The structure of the nanocomposite was confirmed through X-ray diffraction, micro-Raman scattering spectroscopy, Ultraviolet–Visible spectroscopy, and Fourier transform infrared spectroscopy. The structural growth and morphological aspects were analyzed using scanning/transmission electron microscopy, revealing marvelous micro-structural features of the assembled nano-system resembling a maple leaf. To determine the composition, energy dispersive spectroscopy and X-ray photoelectron spectroscopy were used. Microwave magneto-dielectric spectroscopy revealed the improved dielectric properties of the nano-composite compared to those of the parent functional nanocrystals. Temperature gradient dielectric spectroscopy was used over the spectral range from 100 Hz to 5 MHz to reveal the phenomenological effect that the nanosystem flips from its usual semiconductor nature to a metallic nature with sensing temperature. Electrical conductivity and dielectric analysis indicated that the dielectric loss and the dielectric permittivity increased at room temperature. This extraordinary switching capability of the functionalized graphene nanosystem opens up a new dimension for engineering advanced and efficient smart composite materials. [ABSTRACT FROM AUTHOR]

Multi-Gate FET (MGFET) device technology is the most promising technology for extending Moore's Law all the way down to 5nm. Besides being fully compatible with CMOS in both bulk and SOI varieties, MGFET device technology offers excellent solution to the problems of tunnelling carriers through ultra-thin gate dielectrics, short-channel effects, degraded sub-threshold performance and eventual quantum-mechanical effects that plagued planar CMOS as it is scaled down towards 20nm. Furthermore, it offers the ability to operate at much lower supply voltages and allows both static and dynamic power savings. In this paper. Common-mode (CM) MGFETs for three technology nodes (32nm, 22nm and 16nm) were simulated using SPICE simulator and compared for various performance characteristics. The variation in performance parameters was studied and compared for Double-Gate (DG), Triple-Gate (TG) and Gate-All-Around (GAA) to verify their scope for analogue and digital applications. In addition, the comparative results and performance parameters of CM MGFETs based logic gates for the three technology nodes are also presented. [ABSTRACT FROM AUTHOR]

This article investigates the aspects of designing a nanocell based molecular memory. An empirical model for molecular device is developed, based on circuit behavior of nitro-substituted Oligo (Phynylene Ethynylene) molecule (OPE). This device model is subsequently used to design nanocell based 1-bit memory and verified using HSPICE. The approach is extended to train the nanocell for multibit storage capability using external voltage signals. It is observed that to successfully train a 2-bit molecular memory, the number of control signals should be approx. one-fourth of total number of nanoparticles. A computational framework is proposed to compute the probability of retrieving the stored data bits correctly, at the output terminal of the nanocell buffer. This nanocell configuration is simulated by systematically varying number of nanoparticles and molecular switches. It is observed that the probability of the existence of at least one path from input to output approaches close to unity with presence of 20 or more nanoparticles in a nanocell. During memory model validation, 1000 samples of 1-bit memory (consisting of 20 nanoparticles) were generated and verified for read and write operations. The model verification results obtained for this memory cell closely match those obtained using analytical solution of probabilistic graph model. [ABSTRACT FROM AUTHOR]

This work explores anti-serial (anti-parallel) memristive switches-ASMs (APMs)-as potential cross-point elements in nano-crossbar resistive random access memory arrays. The memory operation principles for both device combinations are shown in detail. The effectiveness of these memristive structures to the solution of the parasitic conducting (current sneak paths) problem is presented via an analytical approach which is based on the basic setup of resistive crossbar memories. Simulation results of crossbars of up to 4,096 elements, arranged in quadratic configurations, are conducted. The provided results supplement this comprehensive analysis of APMs and ASMs, outlining their overall performance characteristics and commenting on their applicability to the practical realization of large crossbar memory systems. Finally, a special array topology is applied to an ASM-based crossbar memory. Its performance is compared to the performance of the pure ASM-based memory. The conducted simulations reveal significantly improved read-out voltage margins which further contribute to addressing the parasitic current paths which prevent the reliable operation of memristive crossbar circuit topologies. [ABSTRACT FROM AUTHOR]

The Vertical Strained SiGe Impact Ionization MOSFET incorporating Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The effect of doping concentration for both Source and Drain (S/D) as well as body doping concentration to the performance of VESIMOS-DP in terms of subthreshold slope (S), threshold voltage (VTH) and drain current has been observed in this paper. An inverse proportional of S and VTH value was found when S/D doping concentration increased. It is notable that for S/D doping concentration above 1019 atoms/cm3, there is a significant increase in S values which is not recommended as the switching speed getting higher distracting performance of the device. However, too low S/D doping concentration is not essential as it didn't show any significant improvement on the performance of the device. It is also revealed that with low body doping concentration, the device suffers tremendous Parasitic Bipolar Transistor (PBT) effect that prevents the device from switched off. Thus, optimum doping concentration is imperative to obtain superb device characteristic. Due to the DP layer, a stable VTH =1.35V obtained due to the vicinity of DP layer near the drain end has reduced charge sharing between the source and drain. The slight different and consistency of VESIMOS-DP subthreshold value (S = 19 mV/dec) has given advantages for incorporating DP layer near the drain end. In many aspects, it is revealed that the incorporation of DP has enhanced the electrical performance and suppressed PBT effect of IMOS in the nanometer regime for future development of nanoelectronic device. [ABSTRACT FROM AUTHOR]

Abstract: We construct a molecular junction where propyl contacts two armchair carbon nanotubes through five-member ring and perform the first-principles calculations of its transport properties. The negative differential resistance effect with peak-to-valley ratio of 700% is present. Our investigations indicate that contact transparency can induce negative differential resistance in nanotube–molecule–nanotube junction, which may promise the potential application in nano-electronics devices in the future. [Copyright &y& Elsevier]

Several emerging nano-technologies, including crossbar nano-architectures, have recently been studied as possible replacement or supplement to CMOS technology in the future. However, extreme process variation and high failure rates, mainly due to atomic device sizes, are major challenges for crossbar nanoarchitectures. This article presents variation- and defect-tolerant logic mapping on crossbar nano-architectures. Since variation/defect-aware mapping is an NP-hard problem, we introduce a set of Integer Linear Programming (ILP) formulations to effectively solve the problem in a reasonable time. The proposed ILP formulations can be used for both diode-based and FET-based crossbars. Experimental results on benchmark circuits show that our approach can reduce the critical-path delay 39% compared to the Simulated Annealing (SA) method. It can also successfully achieve 97% defect-free mapping with 40% defect density. It can tolerate process variations to meet timing constraints in 95% of the cases, compared to only 77% achieved by SA. [ABSTRACT FROM AUTHOR]