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In the proposed work, cylindrical Nanowire Field Effect Transistors (NWFETs) are created for sub-10 nm applications using the charge plasma (CP) principle. In the middle of the transistor, a gate is surrounded by an oxide layer and a channel layer. By enclosing the channel in an oxide layer and surrounding it with a distinctive metal layer with various work functions, the charge-plasma concept is introduced. A detailed discussion of device characteristics, such as electric potential and transfer qualities, are presented. For channel lengths of 35 and 10 nm, measurements of the threshold voltage, drain current, and ION/IOFF ratio are analyzed. Sentaurus Technology Computer Aided Design (TCAD) is used to evaluate and analyze the device. TCAD simulations that incorporate the Lombardi mobility model, Shockley-Read-Hall (SRH) model, Density-Gradient model, and Auger recombination models make it easier to calculate tunneling and recombination. Interestingly, the CP-based NWFET produces twice as much output current as its traditional NWFET. Because of the Schottky junction's larger vertical field, significant improvements include the reduction of lateral coupling between the source and drain field lines, the stabilization of the ION/IOFF ratio, an overall reduction in parasitic leakage, and improved scalability. This work extends to circuit implementation, featuring the development of an Inverter circuit. Performance assessments are conducted, and comparisons are drawn with varying channel lengths and widths, further substantiating the efficacy of the proposed structure. [ABSTRACT FROM AUTHOR]

The proposed work focuses on the outcomes brought about by the inclusion of Charge Plasma (CP) concept in a cylindrical Nanowire Field Effect Transistor (NWFET) for sub 10 nm. The Gate is surrounded by an oxide layer, which is further surrounded by a channel layer. The concept of charge-plasma is introduced in the channel by surrounding an oxide layer around the channel, and a different work functions metal layer around the oxide. The performance of device parameters like the electric potential and transfer characteristics have been described. Analysis of Threshold Voltage, drain current and ION/IOFF ratio have been carried for 35 nm and 10 nm channel length. Sentaurus Technology Computer Aided Design (TCAD) has been used to evaluate and analyze this device for sub 10 nm. To calculate tunneling and recombination, the TCAD simulates the Lombardi mobility model, Shockley-Read-Hall (SRH), Density Gradient model, and Auger recombination models. This device generates twice times more output current by using the CP-based NWFET as compared to the conventional NWFET. The parasitic leakage has been reduced and the ION/IOFF ratio has been stabilized. Also, the scalability is enhanced, and the Schottky junction's high vertical field lowers the lateral coupling between the source and drain field lines. This can be used to implement in memory devices such as Inverter, 6T SRAM, 8T SRAM in future. [ABSTRACT FROM AUTHOR]