Search

Recent breakthroughs in Neural Networks (NNs) led to significant accuracy improvements. This accuracy improvement comes at the cost of immense increase in computation demands. NNs became one of the most common and computationally intensive workloads in today's datacenters. To address these computational demands, Google announced in 2016 the Tensor Processing Unit (TPU), an advanced custom ASIC accelerator for NN inference. Two new TPU versions (v2 and v3) followed that support also training. Google TPUv3 packs immense processing power in a tiny and condensed area, leading to very high on-chip power densities and thus excessive temperature. In this work, superlattice thermoelectric cooling, which is one of the emerging on-chip cooling, is considered as an advanced cooling example for Google TPU and we investigate the impact of Negative Capacitance FET (NCFET) on the cooling and efficiency of TPU. Our results demonstrate that NCFET can significantly minimize the required cooling-cost. We explore all NCFET configurations including the thickness of the ferroelectric layer of NCFET, the operating voltage, cooling, and the operating frequency, in addition to all possible FinFET's configurations. Moreover, our experimental evaluation shows that by eliminating the cooling cost, NCFET delivers 2.8x higher efficiency compared to the conventional FinFET baseline.

An enormous study is being carried out in the field of emerging steep slope devices, specifically on negative-capacitance-based and phase transition-based devices. This article investigates the action of ferroelectric (FE) and phase transition material (PTM) on a hybrid device, negative-capacitance-assisted phase transition FinFET (NC-PT-FinFET). We encounter several unique phenomena resulting from this unified action and provide valid arguments based on these observations. A significant enhancement in the differential gain and transconductance, a unique variation in the effect of PTM on drain-channel coupling, tunability of hysteresis across PTM by FE thickness( [Formula: see text]), and ultralow subthreshold slope (SS) by lowering both of its factors are some of the major outcomes of the NC-PT-FinFET. Focus is built on comprehending the individual role of FE and PTM in the intriguing features observed in every device performance parameter with the help of mathematical expressions and physical interpretations. Various tunable parameters present in this hybrid device widen its applicability in digital and memory applications.

Here we demonstrate negative capacitance (NC) characteristics of a ferroelectric-dielectric (FE-DE) capacitor by means of a fully numerical, self-consistent simulation based on the Miller model (MM) and Poisson's equation. Over the years, the Landau model (LM) has been widely used, which fits experimental data of spontaneous polarization versus electric field ( $P-E_{FE}$ ) characteristics using a so-called ``S-curve''; however, it cannot capture different transitions of polarization switching and can also fail to properly represent the material properties of certain FEs. To overcome such limitations of the LM, we have used the MM to simulate an FE-DE capacitor. Even though the MM seemingly fails to show steep switching characteristics due to the absence of the negative slope in the $P-E_{FE}$ curve unlike the LM, our simulation exhibits the NC characteristics of FE-DE capacitors with significant internal voltage amplification. Notably, we explore the effect of different transitions of polarization switching by varying the coercive field of FE within the MM, and exhibit that greater NC characteristics can be achieved with a FE having a more abrupt switching transition. We have also investigated the impact of other material parameters of FE, such as saturation and remnant polarization, on the NC characteristics of FE-DE capacitors. Our results provide comprehensive insight into the mechanism of FE-DE capacitors, suggesting sophisticated engineering of material and device parameters to seek desired performance of NC devices.

In this paper, for the first time, we explained a detailed physical insight for Negative Differential Resistance (NDR) to Positive Differential Resistance (PDR) transition in a ferroelectric-based negative capacitance (NC) FET and also its dependence on the device terminal voltages. Using extensive well-calibrated TCAD simulations, we have investigated this phenomenon on FDSOI NCFET. The NDR to PDR transition occurs due to Ferroelectric (FE) layer capacitance changes from a negative to positive state during channel pinch-off. This, in turn, results in a valley point in the output characteristic (IDS-VDS) at which the output resistance is infinite. We also found that we could alter the valley point location by modulating the vertical Electric field through the FE layer in the channel pinch-off region using body bias (VBB). The interface oxide charges also impacted the NDR to PDR transition, and a positive interface charge results in faster NDR to PDR transition. Further, we have utilized the modulation in NDR to PDR transition due to VBB for designing a current mirror. Results show that the output current (IOUT) variation due to VDS, reduces from ~8% to ~2% with VBB. We have also designed a single-stage common source (CS) amplifier and provided design guidelines to achieve a higher gain in the NDR region. The results obtained using a small-signal model of the FDSOI-NCFET demonstrate that ~25% higher gain can be achieved with the discussed design guidelines in the NDR region compared to the transition region of IDS-VDS. We have also explored the device scaling effect on the amplifier gain and found that ~2.23x gain can be increased with smaller channel length and higher device width.

Recently, integrating ferroelectric materials with nanotransistors such as carbon nanotube field-effect transistors (CNTFETs) has opened new doors for demonstrating a new generation of ultra-miniature circuits and systems. Utilizing the negative differential resistance effect in negative capacitance CNTFETs (NC-CNTFETs) has spurred the efforts for designing ultra-compact ternary circuits and systems similar to their binary structures. This paper presents an ultra-efficient ternary image edge detection hardware using NC-CNTFET technology. The proposed hardware is endowed with a noise reduction circuitry to mitigate the noise effects. Using four 1x 3 kernels and concatenating the image pixels, the proposed ternary hardware has been designed using only 50 transistors. The proposed ternary hardware at the circuit level shows, on average, 74% improvements regarding power delay-product (PDP) compared to the CNTFET-based counterparts. Our comprehensive simulations indicate that the proposed NC-CNTFET-based hardware shows a 40% improvement in data loss, 2.2 times improvement in performance ratio, and 1.14 times improvement in Pratt's figure-of-merit, respectively, compared to the related designs. Our results accentuate that the proposed NC-CNTFET-based ternary hardware is a breakthrough achievement in demonstrating ultra-efficient and noise-immune ternary image processing circuits beyond the conventional binary counterparts.

MoS₂ negative-capacitance field-effect transistors (NCFETs) with a gate-stack of Hf₁₋ₓZrₓO₂/Al₂O₃ are fabricated, and the effects of the Zr content and the thickness of the stacked gate on electrical performance of the devices are investigated. It is found that a large improvement of device performance can be achieved by optimizing these parameters, e.g., using 6-nm Hf $_{0.5}$ Zr $_{0.5}$ O₂ (Zr content of 50%) as a ferroelectric layer and 2-nm Al₂O₃ as a matching layer, the relevant MoS₂ NCFET exhibits the excellent electrical characteristics: a low subthreshold swing (SS) of 31.4 mV/dec, a smaller counterclockwise hysteresis of ~75 mV, and a high on/off current ratio of 3.26 x 10⁶. The involved mechanisms lie in that: 1) an enhanced remnant polarization leads to low SS and 2) changing the thickness of the Hf₁₋ₓZrₓO₂ and Al₂O₃ can adjust the magnitude of ferroelectric capacitance and MOS capacitance to realize a reasonable match between both.

Despite the remarkable development in ferroelectric HfO2-based FETs, key reliability challenges (e.g., retention, endurance, etc.) may still limit their widespread adoption in memory and logic applications. In this paper, we present a simple theoretical framework—based on the Landau theory of phase transition—to design both ferroelectric FETs (FeFETs) and negative capacitance transistors (NCFETs) and investigate their reliability issues. For FeFETs, we analyze the role of interface and bulk traps on memory window closure to quantify endurance under different operating conditions. For NCFETs, we discuss the beneficial role of NC effect in reducing (or even eliminating) the persistent reliability issue of negative bias temperature instability that has plagued MOSFETs for decades. FE/NCFETs can also be affected by the Hot Atom Damage involving switching-induced bond dissociation during transient overshoot. We conclude by discussing how other FET reliability issues (e.g., TDDB, HCD, etc.) may also have to be reinterpreted for FE/NCFETs.

A gate-all-around charge plasma nanowire field-effect transistor (GAA CP NW FET) device using the negative-capacitance technique is introduced, termed the GAA CP NW negative-capacitance (NC) FET. In the face of bottleneck issues in nanoscale devices such as rising power dissipation, new techniques must be introduced into FET structures to overcome their major limitations. Negative capacitance is an efficient effect that can be incorporated into a device to enhance its performance for low-power applications and help to reduce the operating voltage. The Landau–Khalatnikov equation can be applied in such cases to obtain the effective bias. To determine the effects of negative capacitance, lead zirconate titanate (PZT) ferroelectric material, a ceramic material with perovskite properties, is adopted as a gate insulator. This approach diminishes the supply voltage and reduces the power dissipation in the device. Excluding their polarization properties, ferroelectric materials are similar to dielectric materials, and PZT offers abundant polarization with improved reliability and a higher dielectric capacitance. Without proper tuning of the thickness of the PZT material, hysteresis behavior mat occur. Hence, the thickness of the PZT material (tFE) is an essential parameter to optimize the device performance and achieve a reduced threshold voltage for the GAA CP NW NC-FET device proposed herein. Furthermore, varying the thickness of the PZT ferroelectric material can also enhance the performance. When using the highest values of tFE, improved outcomes with an analogously lower operating voltage are observed. The effects of varying tFE on the performance characteristics of the device including the drain current, transconductance, polarized charge, etc. are also interpreted herein.

A negative-capacitance (NC)-induced junctionless gate-all-around (GAA) nanowire field-effect transistor (FET) is proposed by deploying the ferroelectric material (FE) lead zirconium titanate (PZT) between the gate electrode and metal, referred to as the NC JLNWFET. The FE material is used as a gate dielectric in addition to a high-K dielectric. The PZT gate stacking develops a negative capacitance owing to the alignment of dipoles with biasing, which is responsible for improving the direct-current (DC) and linearity performance compared with the conventional JLNWFET. The parameters ION, IOFF, ION/IOFF, and Vth are considered for the DC analysis, whereas gm, gm2, gm3, and VIP2 are considered for the linearity analysis. The results show that ION and the ION/IOFF ratio are improved in the NC JLNWFET by a factor of 12.5 and 6.38. The impact of design parameters such as the channel doping, drain voltage, and interface trap charge on the electrical performance and linearity parameters is analyzed in detail. The improvement in the linearity results in a distortionless structure. The high ION/IOFF ratio and low Vth of the proposed structure mitigate the static and dynamic power in digital circuits and make the device suitable for use in low-power applications. Thus, the proposed NC JLNWFET can be used in distortionless and low-power applications.

Presently Si-based field-effect transistors (FETs) are approaching their physical limit, and further scaling their gate length down to the sub-10 nm region is becoming extremely difficult. Benefitting from the atomic-scale thickness and dangling-bond-free flat surface, two-dimensional semiconductors (2DSCs) have good electrostatics and carrier transportability. The FETs based on the 2DSC channel have the potential to scale the FETs’ gate length down to the sub-10 nm region while avoiding apparent degradation of the device performance. In this review, we introduce the recent experimental and ab initio quantum transport simulation progress in the 2D FETs with a gate length less than 10 nm. Remarkably, in the extremely optimistic condition, many 2D FETs (i.e phosphorene, silicane, arsenene, tellurene, WSe2, InSe, Bi2O2Se, GeSe, etc.) show excellent device performance for the high performance and/or low power applications and indeed can extend Moore’s law down to 1 ∼ 2-nm gate length in terms of the ab initio quantum transport simulation. The sub-10 nm 2D tunneling FETs are predicted to generally have smaller energy-delay products compared with the 2D metal–oxide–semiconductor FETs and appear more competitive for the low power application. The carrier effective mass plays a key role in determining the device performance. Via negative capacitance techniques, the device performance can be further improved. Finally, we outline the challenges and outlook on the future development directions in the sub-10 nm 2D FETs.

In this article, we present a model for the gate tunneling current (GTC) in metal-ferroelectric-insulator-semiconductor (MFIS) negative capacitance FETs (NCFETs), which, to the best of our knowledge, is the first such report. The model is numerical in nature, and is developed using the Tsu–Esaki formulation, employing the Wentzel–Kramer–Brillouin (WKB) approximation, in order to estimate the transmission coefficients of the carriers through the barriers. The ferroelectric (FE) material considered is HfO 2, and is modeled using the Landau phase transition theory. Simulation results reveal a remarkable nonmonotonic dependence of the GTC on the FE layer thickness, an effect that we explain through the Landau model. Furthermore, it is shown how this GTC can be reduced by orders of magnitude without changing the overall dielectric capacitance—a feature that may prove to be beneficial in low-power circuit designs. Additionally, it is seen that the GTC is a weak function of the remanent polarization and coercive field of the FE. All the model predictions are validated through a comparison with the results obtained from Sentaurus 2-D TCAD simulations. The novel results presented in this work should serve as a guide for detailed experimental studies on the gate current characteristics of MFIS NCFETs.

Emerging voltage reference generators (VRGs) are of great demand for low-power applications in recent years. However, keeping good linearity for VRGs in deep submicrometer process is still challenging. Negative capacitance field-effect transistor (NCFET) is an emerging device, which has been found with a negative differential resistance (NDR) phenomenon and has the potential to be applied in VRGs to optimize their linearity. Hence, the feasibility of using NCFET in an emerging ultralow-power (ULP) VRG is studied in this work. An empirical formula to describe NCFET’s NDR is proposed and verified by simulation through a compact SPICE model based on the Landau–Khalatnikov (LK) equation. By adjusting the strength of NDR of NCFET, its output differential resistance can be changed and cancel out the positive differential resistance (PDR) of CMOS transistor. Therefore, the proposed NCFET-based VRG achieves higher linearity. The simulation results show that the line regulation of the NCFET-based VRG decreases from 2.25%/V to 0.21%/V ( $10\times $ ).

Here in, we investigated the impact of negative capacitance in PGP-SELBOX NCFET (partial ground plane on a selective buried oxide in negative capacitance FET) over FDSOI. The ferro-electric layer is placed in the gate stack of PGP-SELBOX NCFET to generate the negative capacitance phenomenon. Ferro-electric(FE) materials are similar to dielectric materials but differ in terms of their polarization properties. FE-HFO2 is used as ferroelectric material due to its sufficient polarization rate with high dielectric capacitance and better reliability. The effect of ferro-electric material parameters like coercive field(Ec) and remnant polarization(PR) on the capacitance matching of NCFET are analyzed. The simulation results reveal that the RPE factor, which is the ratio of PR to Ec, is closely related to better capacitance matching. In addition, the effect of variation in thickness of ferro-electric layer on the average sub-threshold swing(SS) is also explored. The relation between short channel effects (Vth rolloff and DIBL) and thickness of the ferro-electric (tfe) for PGP-SELBOX NCFET is also analyzed. The simulation results clearly show that PGP-SELBOX NCFET is having reduced SCEs and 103 times better $\frac {\mathrm {I}_{\text {ON}}}{\mathrm {I}_{\text {OFF}}}$ ratio over FDSOI NCFET. For optimized value of ferro-electric parameters average SS for proposed device is found as 50 mV/decade at tfe = 5nm which is lesser than FDSOI NCFET (56 mV/decade).

Recently, increasing power leakage has become a major concern especially in MOSFET based nanoscale devices due to poor gate control. To mitigate these problems, the devices with steep slope, low leakage and power consumption are required. In this context, this work introduced a novel concept of Negative Capacitance (NC) effect with Junctionless Multi Gate FET to investigate various device performance parameters for nanoscale dimensions. The baseline approach of combining LK-equation with Sentaurus TCAD tool, was used to design and optimize a 14nm n-type Negative Capacitance Junctionless FinFET (NC-JL FinFET) with doped HfO2 as gate ferroelectric material for low power applications. The impact of ferroelectric thickness, spacer and gate dielectric was analyzed using extensive device simulations. The results showed that the designed NC-JL FinFET exhibits enhanced performance with steep SS, Negative DIBL, lower leakage current and also higher drive current performance than JL FinFET. Further, the application of strain-engineering in NC-JL FinFET shows 12 % improvement in ION/IOFF as compared to unstrained NC-JL FinFET.

The Ultrathin body double gate FE layer TFET(UTB-DG-FE-TFET) is proposed and investigated in this work. Electrical performance parameters such as surface potential ψ(x), electrical field, drain current, sub-threshold swing, threshold voltage, and I on /I off ratio are further analyzed using simulation-based analysis. Integration of Si: HFO 2 ferroelectric layer on top and bottom surfaces make the structure that provides negative capacitance, higher on current, enormous surface potential, peak electric field, and improvement in SS with degradation in off Current. The suggested design is evaluated in comparison with FE-TFET and standard TFET devices. Finally, the impact of device geometry variants like ferroelectric layer thickness (t fe ), intrinsic channel thickness t si , interfacial layer types, interfacial layer thickness (t ox ) and channel length L c on transfer characteristics are investigated through 2D TCAD Sentaurus Simulator for a clear validation of its optimization. The recommended work demonstrates that it is a suitable device enabling superior performance and helpful in ultra-low-power applications.

Bias Temperature Instability (BTI) has always been a critical reliability issue in a field effect transistor (FET). In a negative capacitance (NC) FET, a study of BTI with considering the traps at different interfaces is needed to investigate the device performance, which is not yet explored. In this work, for the first time, we have addressed the individual and the combined effect of bulk traps and the interface traps introduced at different interfaces in an NC fully depleted silicon on insulator (FDSOI) FET. We found: 1) interface Si–SiO2 and SiO2–HfO2 or bulk HfO2 traps nullify the threshold voltage variation and 2) the presence of traps changes the ferroelectric (FE) polarization and in turn vertical field distribution which leads to an increased OFF current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ). Further, it causes the early end of lifetime (EOL) due to bulk HfO2, and HfO2–SiO2 traps for NC FDSOI. These results have been extracted by using a well-calibrated TCAD framework. Since the current amplification and the subthreshold reduction in NC transistors can be achieved by increasing the FE thickness; but in our work, we found that increasing the thickness is not appropriate as the higher FE thickness predominantly degrades the NC device performance, and a thickness optimization is highly required from the reliability perspective.

We propose a parallel negative-capacitance field-effect transistor (P-NCFET) structure, in which a ferroelectric operating in its negative-capacitance region is placed in parallel with the gate and source terminals of a MOSFET. The P-NCFET is stabilized by combining careful matching of the ferroelectric with the gate capacitance along with simple feedback realized using current mirrors. The novel stabilization approach opens the possibility for a variety of new applications that exploit the negative capacitance of ferroelectrics to cancel capacitance in integrated circuits. As an example, we show the P-NCFET structure has a significantly higher unity-current-gain frequency ${f}_{T}$ compared to a conventional MOSFET.

For the first time, we demonstrate an optimization technique to synthesize circuits in the Negative Capacitance FET (NCFET) technology. NCFET is a rapidly emerging technology to replace the currently employed CMOS technology due to its profound ability to overcome the fundamental limit in scaling along with its full compatibility with the existing fabrication process. This is achieved by replacing the traditional transistor gate dielectric with a ferroelectric layer that manifests itself as a Negative Capacitance (NC), which magnifies the electric field. As a result, NCFET-based circuits can operate at a higher clock frequency without the need to increase the operating voltage. NC breaks one of the fundamental laws in physics in which the total capacitance of two capacitors connected in series becomes larger–instead of smaller in ordinary capacitors– than each of them. This could lead to sub-optimal netlists, suffering from significant increase in dynamic power and IR-drops. To suppress that, we employ the relation between delay decrease and capacitance increase of gates w.r.t ferroelectric thickness. Our technique takes an optimized netlist, obtained from commercial EDA tools, and then selectively determines the optimal ferroelectric thickness for each gate in the netlist, so that the maximum performance provided by NCFET is still achieved while the dynamic power is considerably decreased (45% on average), i.e., no trade-offs . Particularly, our technique enables the full exploitation of the performance benefits originating by NCFET, at a significantly lower (power) cost. Compared to state of the art, our technique decreases the energy-delay-product of circuits by 25% on average and reduces the deleterious effects of IR-drop by 56%. Hence, efficiency and reliability of circuits are improved without any loss in the obtained performance from NCFET.

We propose and analyze a dielectric modulated (DM) negative capacitance (NC) fin-field effect transistor (FinFET) based biosensor for efficient and label-free detection of biomolecular entities. For the first time, the NC effect on bio-sensing owing to the presence of a dielectric-ferroelectric gate oxide stack is investigated. First, capability of the NC-FinFET is compared with the baseline FinFET as percentage variation in electrical parameters. Also, the sensing capability of the proposed device is examined with a wide variety of biomolecules with varying dielectric constants. Inclusion of the NC effect in the biosensor exhibits very high sensitivity in terms of the electrical figures of merit (FoMs) such as threshold voltage, $I_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ -ratio, output conductance, and intrinsic gain with rapid response because of the steep subthreshold value. The use of raised source drain (RSD) architecture allows more cavity space to the biomolecules and, hence, increases the sensitivity and selectivity of the biosensor. All the device simulations are performed in a 3-D Sentaurus TCAD environment using well-calibrated structure. To establish a benchmark, the sensitivity of the proposed biosensor is also compared with the published literature in order to determine its effectiveness. The results of this study can establish NC-FinFET as a viable candidate for label-free DM biosensor applications.

We theoretically investigated the effect of interface traps ( ${D}_{it}$ ) at the Si/SiO2 interface on the transient negative capacitance (NC) effect of the ferroelectric (FE) FETs. We used a metal/FE/interlayer/Si (MFIS) capacitor in series with a resistor to simulate the NC effect. Our simulation results show that appropriate ${D}_{it}$ can further improve the subthreshold swing (SS) by tuning the mismatch of the switching rate between free charges ( ${Q}_{f}$ ) and polarization charges ( ${P}$ ). In addition, we also analyzed the impact of different circuit parameters on the device performance. The following device design can improve the SS characteristics: thicker FE layer, thinner interlayer (DE), lower external resistance, and larger viscosity coefficient.

In this work, we report that the AFE/FE gate-stack can be utilized to engineer the S-curve for boosting the ION of NC-FinFET. By using a short-channel BSIM-CMG compatible AFE/FE stack NC-FinFET model, the capacitance matching and ON-state performance for AFE/FE stack NC-FinFETs are investigated. Our study indicates that, the AFE/FE gate-stack can be used to improve the capacitance matching in strong inversion at higher gate-bias. Therefore, impressively higher ON-state current (compared to single-layer) can be achieved. In reality, source-drain series resistance will make such high IDS impractical. The more likely strategy is to use lower VDD to achieve much lower power consumption (and reduced vertical fields). While the transient NC effect also needs to be carefully investigated, this study suggests significant long term benefits to VDD scaling if materials with certain AFE and FE properties are developed and introduced in IC manufacturing in the future.

In this paper, a novel third-order autonomous memristor-based chaotic circuit is proposed. The circuit has simple topology and contains only four elements including one linear negative impedance converter-based resistor, one linear capacitor, one linear inductor, and one nonlinear current-controlled memristor. Firstly, the voltage-current characteristic analysis of the memristor emulator for different driving amplitudes and frequencies are presented. With dimensionless system, the symmetry, equilibrium point and its stability are analysed. It is shown that the system has two unstable saddle-foci and one unstable saddle. A set of typical parameters are chosen for the generation of chaotic attractor. Differing from the common period-doubling bifurcation route in smooth dynamical systems, this memristive system shows abrupt transition from the coexisting period-1 limit cycles to robust chaos when varying system parameters. Various dynamical behaviors are analysed using the numerical simulations and circuit verifications.

Understanding the operation of neurons and synapses is essential to reproducing biological computation. Building artificial neuromorphic networks opens the door to a new generation of faster and low-energy-consuming electronic circuits for computation. The main candidates to imitate the natural biocomputation processes, such as the generation of action potentials and spiking, are memristors. Generally, the study of the performance of material neuromorphic elements is done by the analysis of time transient signals. Here, we present an analysis of neural systems in the frequency domain by small-amplitude ac impedance spectroscopy. We start from the constitutive equations for the conductance and memory effect, and we derive and classify the impedance spectroscopy spectra. We first provide a general analysis of a memristor and demonstrate that this element can be expressed as a combination of simple parts. In particular, we derive a basic equivalent circuit where the memory effect is represented by an RL branch. We show that this ac model is quite general and describes the inductive/negative capacitance response in many systems such as halide perovskites and organic LEDs. Thereafter, we derive the impedance response of the integrate-and-fire exponential adaptative neuron model that introduces a negative differential resistance and a richer set of spectra. On the basis of these insights, we provide an interpretation of the varied spectra that appear in the more general Hodgkin–Huxley neuron model. Our work provides important criteria to determine the properties that must be found in material realizations of neuronal elements. This approach has the great advantage that the analysis of highly complex phenomena can be based purely on the shape of experimental impedance spectra, avoiding the need for specific modeling of rather involved material processes that produce the required response.

This paper reports dynamical effects in one-dimensional locally resonant piezoelectric metastructures leveraged by nonlinear electrical attachments featuring either combined quadratic and quartic, or essentially quartic potentials. The nonlinear electromechanical unit cell is built upon a linear host oscillator coupled to a nonlinear electrical circuit via piezoelectricity. Semi-analytical harmonic balance (HB)-based dispersion relations are derived to predict the location and edges of the nonlinear attenuation band. Numerical responses show that weakly and moderately nonlinear piezoelectric metastructures (NPMSs) promote a class of nonlinear attenuation band where a bandgap and a wave supratransmission band coexist, while also imparting nonlinear attenuation at the resonances around the underlying linear bandgap. Besides, strongly nonlinear regimes are shown to elicit broadband chaotic attenuation. Negative capacitance (NC)-based essentially cubic piezoelectric attachments are found to expand the aforementioned effects over a broader bandwidth. Excellent agreement is found between the predictions of the HB-based dispersion relations and the nonlinear transmissibility functions of undamped and weakly damped NPMSs at weakly and moderately nonlinear regimes, even in the presence of NC circuits. This research is expected to pave the way toward fully tunable smart periodic metastructures for vibration control via nonlinear piezoelectric attachments.

Optical analysis is critical for evaluating light-emitting diodes (LEDs), and previous studies have been done on the relationship between negative capacitance of LEDs and how to improve luminous efficiency. In this study, optical studies were performed on LEDs of different colors. Luminous intensity is related to frequency. The lower the frequency, the greater the relative luminous intensity, and the luminous intensity basically tends to be saturated. When the relative luminous intensity is within a certain range, the negative capacitance is related to the luminous intensity in a logarithmic relationship. Meanwhile, the relation between negative capacitance and the luminous intensity under different voltages is the same. From the comparison between the luminescence experiment and the previous capacitance characteristics experiment, it can be concluded that the final effect caused by other factors affecting the frequency characteristics of the capacitance is that the composite capacitance exhibits a hysteresis effect, and the lower the frequency, the more obvious the lag. Therefore, the appearance of negative capacitance is not just caused by recombination; there must be other factors.

In this work, we perform the sensitivity analysis of negative-capacitance (NC) junctionless (JL) transistors considering the variation in device parameters and compared its performance with conventional JL devices. The OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) of the JL transistor degrades significantly as the film thickness ( ${T}_{{\text {si}}}$ ), channel doping ( ${N}_{\text {ch}}$ ), and oxide thickness ( ${T}_{\text {ox}}$ ) increase and the gate length ( ${L}_{g}$ ) decreases. However, compared to JL devices, ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ degradation due to increasing ${T}_{\text {si}}$ and ${N}_{\text {ch}}$ and decreasing ${L}_{g}$ can be effectively mitigated in NCJL devices. The reduced ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ and lower $I_{ \mathrm{\scriptscriptstyle OFF}}$ sensitivities in the NCJL transistor are due to the occurrence of more negative internal gate voltage at higher ${T}_{{\text {si}}}$ and ${N}_{{\text {ch}}}$ and lower ${L}_{g}$ , which enhances the channel depletion and reduces the ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ sensitivity. The impact of ${T}_{{\text {ox}}}$ and the spacer permittivity ( $\varepsilon _{s}$ ) shows that reducing ${T}_{\text {ox}}$ and increasing $\varepsilon _{s}$ significantly improve the ON-current in NCJL devices due to better capacitance matching at the ON-state. Besides, for the first time, a design methodology is proposed to optimize the NCJL device for high-performance (HP) applications at ${L}_{g} = {15}$ nm. The results presented in this article serve as a guideline to extend the usability of NCJL devices for HP applications.

The incorporation of Si doped HfO2 in negative capacitance electrostatically doped TFET realizes ultra-steep and process variation resistant structure. Here, Si:HfO2 is the gate stack ferroelectric material is used in conjunction with a high-K gate dielectric HfO2/TiO2. The conceptualization of intrinsic gate voltage amplification due to the alignment of ferroelectric dipoles comprehends the negative capacitance (NC) behavior. Moreover, the work-function difference between the source/drain electrodes and the silicon induces electrostatic doping. Thus, the detrimental doping related issues, heavy doping governed mobility degradation and statistical random dopant fluctuations (RDFs) can be eliminated and it results in more process variations immune design. This work has explored the impact of the symmetric and asymmetric structure of the considered devices on both the drain and source sides, in terms of the oxide thickness between the electrodes and the Si body. Here, analog/RF performance estimation is also carried out for the parameters such as transconductance (gm), output conductance (gd), unity gain frequency (fT), intrinsic gain (AV), transconductance frequency product (TFP), and gain frequency product (GFP), etc. Our study reveals that Si:HfO2 ferroelectric gate stack with TiO2 dielectric shows better device performance than Si:HfO2 ferroelectric gate stack with HfO2 dielectric for both dc as well as ac performance.

A dynamic current model for the double gate negative capacitance field-effect transistor (NCFET) of the metal–ferroelectric–insulator–semiconductor (MFIS) structure is presented in this work. With a damping parameter $\rho $ in the Landau–Khalatnikov (LK) theory for general ferroelectric (FE) materials, the gate control equation of NCFET is intrinsically dynamic which is solved directly as a basis of NCFET modeling. With the time-dependent charge densities at the source and drain sides, a dynamic current model is formulated analytically for the first time, considering the dynamic terms in a self-consistent way. The model has been verified with numerical TCAD simulations. It accurately reproduces the static negative capacitance (NC) effect in enhancing the driving current, as well as the dynamic NC effect, in the conduction delay and hysteresis for a wide range of NCFET parameters. The dynamic model after implementations is successfully applied to circuit simulations such as ring oscillators without convergence issues.

A multivalued logic (MVL) device can achieve greater data density with a smaller footprint than a traditional binary logic device. In this study, a ternary logic inverter based on negative capacitance FETs (NCFETs) without additional footprints has been realized. By enhancing the amplification in surface potential owing to the utilization of the negative capacitance, the third intermediate state can be successfully obtained at ${V}_{\text {DD}}$ /2 in the conventional binary CMOS inverter. The third intermediate state arises due to no-saturation effect of drain current, and the noise margin of the third intermediate state (NM $_{M}$ ) can be optimized by changing ferroelectric thickness or annealing temperature of ferroelectric material. The influence of remnant polarization ( ${P}_{r}$ ) and coercive electric ( ${E}_{C}$ ) variation on the ternary logic inverter was investigated based on experimental data. Moreover, a ternary logic 8T SRAM with transmission gate logic (TGL) was proposed, and the results show that the proposed 8T SRAM cell exhibits nondestructive read and reliable write operations for all three states.

This article focuses on how to improve the negative capacitance (NC) properties of NMOSFET in the gate-last process flow. The impacts of the HfZrO ferroelectric film thickness, metal gates with different work functions, stress of filled metal gate, the thickness of seed layer underneath HfZrO etc. on NC effect are investigated, and the corresponding possible mechanisms are discussed. These techniques have been successfully applied to the fabrication of NC-NMOSFETs with physical thickness 1.5-nm HfZrO, and underneath with 1.0-nm ZrO2 seed layer. The NC-NMOSFETs with much improved subthreshold swing (SS) of 38.6 mV/decade and nearly hysteresis free are developed with a gate length of 900 nm, and the SS is over 40 mV/decade smaller than that of the control-2 NMOSFETs with 2.5-nm HfO2 gate dielectric only.

In this work, a quasi-antiferroelectric (QAFE) model to precisely evaluate the electrical characteristics of negative capacitance Fin field-effect transistor (NC-FinFET) integrated with a QAFE gate insulator is proposed. A comparative study of the performance of transistors with ferroelectric (FE) and QAFE of different component ratios is carried out by combining the QAFE model and the BSIM-CMG model. The results demonstrate that the introduction of the QAFE gives rise to performance improvements than those of conventional FinFETs, which is ascribed to QAFE’s negative slope segment of polarization ( ${P}$ ) versus voltage ( ${V}$ ) around ${P} =0$ for the QAFE NC-FinFETs. Because of the induced negative gate charges due to fringing electric field ( ${E}$ ) coupling in the short channel of 3-D FinFET, subthreshold swing (SS) is just slightly lower than the tyrant limit of 60 mV/decade but a significant on-state current enhancement is found in the QAFE NC-FinFETs. The charge range, where the NC effect exists, shows a significant impact on the performance of the device due to the small remnant polarization of the QAFE layer. With the designed component ratio, a superior current enhancement can be obtained compared with the control device. This work provides a design guideline for the development of future high-speed and low-power NC-FinFET with QAFE material.

A superjunction insulated gate bipolar transistor (SJ-IGBT) featuring a self-adaptive hole-extracting (SAHE) path is proposed and investigated by simulation. The SAHE path is formed by a narrow p-type mesa between the two trench gates. In the ON-state, the p-type mesa is depleted by the trench gates and the hole path is pinched off so as to maintain high injection efficiency, and thus a low ON-state voltage ( ${V}_{ \mathrm{\scriptscriptstyle ON}}{)}$ is achieved. During the turn-off period, the p-type mesa recovers into neutral region adaptively and then the hole-extracting path is opened, which helps decrease the turn-off loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ) and suppress the dynamic avalanche. Moreover, at the initial turn-on stage with the SAHE path opening, the P-pillar in the proposed device is shorted to the emitter electrode rather than floating, which suppresses the negative capacitance effect. Therefore, compared with the SJ-IGBT with floating P-pillar, the SAHE SJ-IGBT not only achieves better ${V}_{ \mathrm{\scriptscriptstyle ON}}\!\!-\!{E}_{ \mathrm{\scriptscriptstyle OFF}}$ tradeoff but also reduces the surge current by 23% at the turn-on stage and obtains better controllability on the turn-on $dV_{{\text {CE}}}$ / dt and $dI_{C}$ / dt characteristics, greatly decreasing the electromagnetic interference (EMI).

In this work, we analyze the impact of self-heating effects (SHEs) on 14-nm negative capacitance (NC)-FinFET performance from device to the circuit level. The 3-D thermal TCAD simulations, after careful calibration with measurements, are performed to analyze the impact of SHE in a broad range of frequency. Furthermore, we use the TCAD calibrated BSIM-CMG model to analyze the impact of SHE in NC-FinFET at the circuit level, after including a physics-based model to capture the NC effect. For the first time, we analyze the impact of a nonuniform distribution of temperature dissipated from the channel region to gate-stack in NC-FinFETs. On account of the thermal insulating properties of the gate-stack, the ferroelectric (FE) layer is found to be cooler than the channel region under the impact of SHE. We demonstrate that neglecting that and, hence, using the channel temperature to evaluate the temperature-dependent parameter $\alpha $ (in the Landau–Khalatanikov model of NC effect) of the FE layer result in a significant overestimation of SHE-induced degradations, such as in the NC voltage gain. Based on our TCAD analysis, we propose a relation between gate-stack temperature and the channel temperature and use this to accurately model the $\alpha $ parameter and, hence, SHE in NC-FinFETs. The SHE is found to dominate for both FinFET and NC-FinFET in the gigahertz range, which eventually degrades the performance at the circuit level, which is further confirmed using ring oscillator (RO) simulations.

In this article, we analyze how a ferroelectric (FE) acts as a rechargeable energy storage medium which stores, releases, and retrieves energy, and helps the gate achieve a desired charge density with reduced energy (voltage) from the external gate drive. During transistor turn-on, the FE releases energy, while the whole system is absorbing energy, and during turn-off, the FE retrieves energy, while the whole system is releasing energy. Capacitor energy is analyzed using two different approaches: static material free energy integrals and transient circuit power integrals. The two results agree within 1%. Energy analysis is also performed for a metal–oxide–semiconductor field-effect transistor structure for two gate lengths, 20 nm and $2~\mu \text{m}$ , in an inverter circuit. At 2- $\mu \text{m}$ gate length, the values of energy match under these two different approaches with less than a 6% difference. The difference is larger in the 20-nm gate length case due to larger parasitic capacitances, such as gate-to-drain and gate-to-source capacitance, affecting the transient circuit analysis. Even so, most of the energy storage and retrieval benefit is retained even in small size negative capacitance transistors.

Approximate computing is established as a design alternative to improve the energy requirements of a vast number of applications, leveraging their intrinsic error tolerance. Voltage over-scaling (VOS) is one of the most energy-efficient approximation techniques, but its exploitation is still limited due to the large errors it induces. In this work, we investigate, for the first time, the resiliency of negative capacitance transistor (NCFET) technology to VOS in comparison to conventional CMOS technology. Our work reveals that circuits implemented using the NCFET technology exhibit much less timing errors under VOS due to the inherent voltage amplification provided by the ferroelectric layer. NCFET is one of the very promising emerging technologies that is rapidly evolving for low-power circuit as it enables the transistors to switch faster without the need to increase the voltage. We demonstrate how NCFET technology allows circuit designers to effectively employ VOS to boost the efficiency of their approximate circuits, while still keeping the induced errors marginal. Our analysis shows that the VOS-resilience of NCFET circuits enables maximizing the voltage decrease and thus, NCFET based VOS approximate circuits achieve from $1.83\times$ up to $2.78\times$ higher energy reduction compared to the corresponding FinFET circuits for the same error bounds.

Measurements on ultrathin body negative-capacitance (NC) field-effect transistors are shown to display subthreshold behaviors that cannot be explained as a classical MOSFET. Subthreshold swing (SS) at low drain bias decreases with increased gate bias for devices measured over multiple gate lengths down to 30 nm. In addition, improvement in the SS relative to control devices shows a nonmonotonic dependence on the gate length. Using a Landau–Khalatnikov ferroelectric (FE) model calibrated with measured Capacitance-Voltage and combining it with TCAD simulations, we show that these anomalous behaviors can be quantitatively explained and interpreted as field-induced permittivity enhancement. The model predicts substantial scaling improvement at the end of the roadmap.