Search

Summary: The ray‐tracing algorithm is very costly regarding time complexity and while many techniques have been conceived over the years with the purpose of accelerating its execution, one stands out: parallelism exploitation of ray‐triangle intersection operations. In this sense, field‐programmable gate arrays (FPGAs) have plenty resources to run specialized accelerators that execute multiple operations in parallel. Moreover, modern FPGAs are embedded with multiprocessor systems‐on‐chip based on ARM architecture, which can be used simultaneously with the FPGA programmable logic to further accelerate the application execution. In this work, we present and analyze a reconfigurable accelerator for ray‐tracing specialized in computing ray‐triangle intersections at the network edge of a heterogeneous cloud computing environment. The accelerator is specified using Xilinx high‐level synthesis and is implemented in a Xilinx Zynq FPGA (XC7Z020‐1CLG400C). We also present an execution model which enables the exploitation of the available computing elements of the heterogeneous system: ARM Cortex‐A53, FPGA programmable logic, and cloud machines. Experimental performance and synthesis results show that the heterogeneous system can efficiently render a simplified version of the Stanford Bunny model when using the hardware accelerator with up to six instances of a ray‐triangle intersection unit together with the other computing resources. [ABSTRACT FROM AUTHOR]

Summary: This article presents a high‐level synthesis implementation of the longest common subsequence (LCS) algorithm combined with a weighted‐based scheduler for comparing biological sequences prioritizing energy consumption or execution time. The LCS algorithm has been thoroughly tailored using Vivado High‐Level Synthesis tool, which is able to synthesize register transfer level (RTL) from high‐level language descriptions, such as C/C++. Performance and energy consumption results were obtained with a CPU Intel Core i7‐3770 CPU and an Alpha‐Data ADM‐PCIE‐KU3 board that has a Xilinx Kintex UltraScale XCKU060 FPGA chip. We executed a batch of 20 comparisons of sequences on 10k, 20k, and 50k sizes. Our experiments showed that the energy consumption on the combined approach was significantly lower when compared to the CPU, achieving 75% energy reduction on 50k comparisons. We also used the tool proposed in this article to do a case study on Covid‐19, with real SARS‐CoV‐2 sequences, comparing their LCS scores. [ABSTRACT FROM AUTHOR]

Summary: Instruction Reuse is a technique adopted in Von Neumann architectures that improves performance by avoiding redundant execution of instructions when the result to be produced can be obtained by searching an input/output memoization table for such instruction. Trace reuse can be applied to traces of instructions in a similar fashion. However, those techniques are yet to be studied in the context of the Dataflow model, which has been gaining traction in the high performance computing community due to its inherent parallelism. Dataflow programs are represented by directed graphs where nodes are instructions or tasks and edges denote data dependencies between tasks. This work presents Dataflow Dynamic Task Memoization (DF‐DTM), a technique that allows the reuse of both nodes and subgraphs in dataflow, which are analogous to instructions and traces, respectively. The potential of DF‐DTM is evaluated by a series of experiments that analyze the behavior of redundant tasks in five relevant benchmarks, where up to 99.70% of the instantiated tasks could be reused. Moreover, this paper evaluates how reuse rates can be affected by limiting subgraph size, memoization table size, task granularity, and problem size, showing that DF‐DTM can yield good reuse rates in more realistic environments. [ABSTRACT FROM AUTHOR]