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In this paper, the susceptibility of a Kuijk bandgap voltage reference to electromagnetic interferences (EMIs) superimposed to the power supply is investigated. A model of the bandgap circuit is derived from experimental tests consisting of scattering parameters and susceptibility measurements on a test chip. The model is able to correctly predict the susceptibility of the circuit by means of SPICE transient simulations. The simulations identify the fundamental stray components responsible for EMI coupling that are usually not taken into account in postlayout analyses. From the EMI point of view, the rectification phenomenon of bipolar transistors, used in the bandgap cell, and the operational amplifier (op-amp) input distortion are shown to cause the voltage reference performance degradation. In particular, for the first time, the importance of the bandgap cell is pointed out, suggesting that the measures to reduce the susceptibility of the op-amp may not be sufficient to guarantee the bandgap immunity. Moreover, the analyses of main parasitic paths (from the power supply net to the more sensitive nodes) demonstrate the relevance of paths that are not commonly considered during the design phase and that may lead to an immunity degradation. Possible solutions to reduce the bandgap susceptibility are also explored, suggesting design criteria, filtering techniques, and layout variations. A second test chip is designed and manufactured to validate the suggested improvements and verify the critical role of the bandgap cell. Finally, a simplified theoretical analysis, which allows a fast bandgap susceptibility evaluation, is presented. This tool is used to point out the importance of the rectification phenomenon compared to the op-amp differential pair distortion. Index Terms--Differential pair distortion, Kuijk bandgap, RF interference, rectification, stray components.

A fully integrated solution for rejecting the interference caused by Wireless Local Area Network transmissions in the 4.9-5.825-GHz band for ultra-wide-band (UWB) receivers is presented. Front-end prototypes implemented in a low cost 0.35-[micro]m SiGe BiCMOS technology are used as a test vehicle to assess the effectiveness of the presented approach. The proposed blocker filtering technique mitigates the gain desensitization, third-order intermodulation distortion and second-order intermodulation distortion by as much as 9.8, 7.9, and 6 dB, respectively. At a power consumption of only 49.2 mW, the receiver conversion gain ranges from 22-19 dB while the double side-band NF measured at the PCB connectors ranges from 5.5-8 dB in the 3.6-7.4-GHz frequency range. Index Terms--BiCMOS integrated circuits, interference suppression, microwave receivers, notch filters, ultra-wide-band (UWB) systems.

In this brief, we propose to use a transformer-based resonator to build a dual-mode oscillator, e.g., a system capable of oscillating at two different frequencies without recurring to switched inductors, switched capacitors, or varactors. The behavior of the resonator configured as a one-port and a two-port network is studied analytically, and the dependence of the quality factor on the design parameters is thoroughly explored. These results, combined with the use of traditional frequency tuning techniques, are applied to the design of a wide-band voltage-controlled oscillator (VCO) that covers the frequency range 3.6-7.8 GHz. The performance of the designed VCO, implemented in a digital 0.13-[micro]m CMOS technology, has been studied by transistor-level and 2.5D electromagnetic simulation (Agilent Momentum). A typical phase noise performance at 1-MHz offset of -104 dBc/Hz has been predicted, while the power consumption ranges from 1 to 8 mW, depending on the VCO configuration. Index Terms--Feedback, microwave oscillators, reconfigurable architectures, transformers, voltage-controlled oscillators (VCOs).

In this paper, we present an all-analog implementation of the rate-l/3, block length 40, universal mobile telecommunications system (UMTS) turbo decoder. The prototype was designed and fabricated in 0.35 [micro]m complementary metal-oxide-semiconductor technology and operates at 3.3 V. We also introduce a discrete-time first-order model for analog decoders which allows fast bit-error rate simulations, while taking into account circuit transient behavior and component mismatch. The model is applied to the rate-l/3 analog turbo decoder for UMTS defined in the Third Generation Partnership Project standard, and the discrete-time model predictions are compared with the decoder experimental performance and the transistor-level simulations. These results demonstrated that this model can be successfully used as a tool to both predict analog decoder performance and give design guidelines for complex decoders, for which circuit-level simulations are impractical. Index Terms--Analog decoding, device mismatch, discrete-time model, iterative decoding, turbo codes.

This work proposes an architecture for an analog-to-digital converter intended for a multimode wireless receiver. The architecture is based on the cascade of a single-bit 2-1 sigma-delta modulator and a 4-bit flash converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence, the proposed converter can fulfill the requirement of a wide range of standards: Global System for Mobile Communications (GSM), Bluetooth, universal mobile telecommunications system (UMTS), and wireless local area network (WLAN)a. The paper discusses extensively the effects of circuit nonidealities on the converter performance, in order to single out the most suited setup for the programmable parameters and to demonstrate the practical feasibility of the proposed system. The converter figures of merit have been quantified by means of transistor-level and behavioral simulations: the achieved dynamic range is 85, 72, 62, and 59 dB for GSM, Bluetooth, UMTS, and WLANa, respectively. The corresponding power consumption is 4.6, 5.5, 7.4, and 18.9 mW. Index Terms--Analog-digital conversion, CMOS analog integrated circuits, delta-sigma ([DELTA][SIGMA]) modulation, radio receivers, sigma-delta ([DELTA][SIGMA]) modulation, wireless systems.

Implantable biomedical devices can highly benefit from submicrometer CMOS technologies both in terms of duration-time increase and size shrinking. This paper shows how design techniques for submicrometer CMOS technologies lead to improvements in the sensing stage of a cardiac implantable pacemaker. A sigma-delta modulator is presented for 8-bit quantization of the natural electrical activity of the heart, fabricated in a 0.8-[micro]m CMOS technology. The low-voltage, low-power design procedure employs switched-opamp and weak inversion CMOS circuits. Measurement results confirm a power dissipation of 1.8 [micro]W, a minimum supply voltage of 1.8 V, and more than 50 dB of dynamic range. Index Terms--Sigma delta ([SIGMA][DELTA]), low power, pacemaker.

A programmable-gain preamplifier and filter for detection of spontaneous heart activity in an implantable cardiac pacemaker is presented. The system is fully integrated in a standard 0.35-[micro]m CMOS technology, including all auxiliary circuits. Two channels are available in order to process both atrial and ventricular signals. CMOS translinear circuits, with particular emphasis on log-domain techniques, have been exploited in order to contain current consumption and to allow correct operation with a reduced supply voltage, due to battery discharging. Indeed, the realized system can operate down to 1.8 V of supply voltage and dissipates at most 1.8 [micro]A, granting at least 47 dB of dynamic range (DR) for the atrial chain, which is compatible with advanced digital sensing. Current consumption can be further reduced at the expense of DR if a simpler sensing like peak detection is adopted. All system performance have been verified by measurements results and are compatible with the requirements of cardiac pacemakers. This work, therefore, demonstrates how a proper design approach, exploiting low-power and low-voltage techniques, allows one to optimize performance for the cardiac pacemaker. Index Terms--Biomedical, companding, log domain, low power (LP), low voltage (LV), pacemaker, translinear (TL) circuits.

The on-state and off-state breakdown voltages of Ga0.47In0.53As composite-channel high electron mobility transistors with variable Ga0.47In0.53As layer thicknesses of 30, 50 and 100 angstrom are studied. Results show that reduced channel thickness improves both on-state and off-state breakdown voltages. On-state breakdown voltages improvements are attributed to increased channel effective energy-gap and a possible decrease in longitudinal electric field. Off-state breakdown voltages improve due to reduced electron sheet density and electric field at the gate edge.

Research has established a novel technique to estimate charge injection and hot carrier effects in self-aligned, etched-polysilicon, npn bipolar transistors with silicon dioxide sidewall emitter spaces. The method estimates maximum electric field changes in the base-emitter junction space charge region at the silicon/sidewall oxide interface.

A survey of hot electron effects occurring in low current density-operated AlGaAs/GaAs heterojunction bipolar transistors provides accurate characterization of impact ionization effects. It uses Monte Carlo simulations to model the carrier distribution functions. Measurements of the base current changes give an estimate of impact ionization whereas simulations demonstrate the influence of dead-space effects on the device multiplication factor. Simulations optimize the collector composition and doping profile, and provide a way out of the breakdown-speed dilemma.

An analysis of the behavior of measured gate current in connection with gate-to-source voltage in depletion-mode double-implant gallium arsenide metal semiconductor field-effect transistors is presented. Results show that a significant impact-ionization generation affects the gate current while the contributions of thermal generation and tunneling are insignificant. The holes produced by impact-ionization are collected at the gate and substrate contacts.

In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as [V.sub.T] and [I.sub.DSS], increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network. Index Terms--Clock skew, manufacturability, mismatch, process variations, statistical design, timing analysis.

The impact of process fluctuations on the variability of deep submicron (DSM) very large scale integration (VLSI) circuit performances is investigated in this paper. In particular, we show that as process dimensions scale down in the subhalf-micron region, the relative weight of process variability tends to increase, thus wearing down a non negligible portion of the benefits that are expected from minimum feature size scaling. We will show that in order to better exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling, as the one described in [1] [assigned probability technique (APT)]. The application of the APT technique to different test circuits designed in 0.35, 0.25, and 0.18 [micro]m CMOS technologies with a power supply ranging from 3.3 V down to 1 V will demonstrate how the manufacturability of DSM designs is going to be a vital factor for the successful implementation of high-performance or low-power systems in 0.18 [micro]m and lesser technologies. Index Terms--Assigned probability, performance spread, process fluctuation, statistical design, worst case model.