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This paper proposes a decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes, aiming to improve the error rate performance for NAND flash memory. Several NB-LDPC decoding methods for NAND flash memory have been studied. Some approaches rely on hard decisions, and these are relatively simple but do not have a good error rate performance. Others are based on soft decisions that require multiple reads for each flash memory cell, leading to significant memory throughput degradation. To improve the error rate performance without suffering performance degradation owing to multiple reads, an iterative pseudo-soft-reliability-based decoding algorithm is proposed. Using Galois field addition to calculate the Hamming distance at the initialization, the proposed algorithm not only improves the error rate performance but also reduces the average number of iterations compared with those of conventional hard-decision-based decoding algorithms.

Short cycles in a nonbinary low-density parity-check (NB-LDPC) code may be even more harmful to its performance if they do not satisfy the so-called full rank condition (FRC). This is because they may induce low-weight codewords or absorbing sets in that case. Thus, it is important to count the number of short cycles not satisfying the FRC as well as the number of short cycles for analyzing the performance of an NB-LDPC code. In this paper, we first develop a novel message-passing algorithm and identify how it is related to the FRC. We then propose a low-complexity algorithm for counting the number of short cycles not satisfying the FRC in an NB-LDPC code, as well as the number of short cycles. Finally, we propose a low-complexity algorithm for designing an NB-LDPC code with low error floor. Depending on the modulation scheme, the codes constructed by the proposed design algorithm have similar or slightly worse performance, compared with those constructed via the method by Poulliatet al.However, the proposed design algorithm does not require a cycle enumeration algorithm with high complexity, and therefore is feasible even in the case of large code length, say ${\geq}5000$. [ABSTRACT FROM AUTHOR]

A simplified version of the enhanced serial generalized bit-flipping algorithm is proposed in this brief. This new algorithm reduces the quantity of information that is stored with a negligible performance loss of 0.05 dB compared with previous proposals. In addition, the algorithm allows us not only to save memory, but also to reduce the number of arithmetic resources needed. In addition, a new initialization of the algorithm avoids using techniques to control data growth without any performance degradation, reduces routing, increasing the maximum frequency achievable, and saves logic. The decoder derived from the simplified algorithm requires almost half the area of previous architectures, with a throughput of 716 Mbps on a 90-nm CMOS process for the (837, 723) nonbinary code over GF(32) at ten iterations. [ABSTRACT FROM AUTHOR]

In this brief, a shuffled schedule (SS) of the min-max decoding algorithm is proposed for nonbinary low-density parity-check (LDPC) codes. To increase the throughput and reduce the memory requirement, a modified SS (MSS) with much simpler check node processing is also proposed, based on a new shuffled merge algorithm. Numerical simulations for three LDPC codes with different lengths and rates over GF(32) show: 1) both SS and MSS converge faster and have slightly better error performance than the flooding schedule, and 2) the degradation of the MSS in error performance as well as convergence rate is negligible. Finally, an efficient decoder architecture based on the MSS is proposed for quasi-cyclic LDPC codes. The proposed decoder architecture further enhances the decoding throughput with improved check and variable node processing units. The implementation results of an (837, 726) LDPC decoder over GF(32) demonstrate that the proposed architecture outperforms those in previous works. [ABSTRACT FROM PUBLISHER]

Prevalent adaptive modulation and coding (AMC) techniques can facilitate the flexible strategies subject to the dynamic channel quality. It would be quite intriguing for one to build a blind encoder identification technique without spectrum-efficiency sacrifice for AMC transceivers. In this paper, we make the first-ever attempt to tackle the blind nonbinary low-density parity-check (LDPC) encoder identification given a predefined encoder candidate set over the Galois field \mathds{GF}(q) for q-ary quadrature amplitude modulation (q-QAM) signals. Our proposed method establishes the log-likelihood ratios (LLRs) of syndrome a posteriori probabilities (APPs), which specify the potential correctness of the underlying parity-check relations, and identifies the nonbinary LDPC encoder leading to the maximum average LLR over the candidate set. Monte Carlo simulation results verify the effectiveness of our proposed new scheme. [ABSTRACT FROM PUBLISHER]

Lattice‐reduction‐aided (LRA) preequalisation for the multiple‐input/multiple‐output broadcast channel has most often been considered for the uncoded case so far. However, recent advantages in the closely related field of integer‐forcing equalisation, where the cancellation of the multiuser interference and the channel coding are combined, create doubt to this separated point of view. In this Letter, the philosophy of matching both the channel code and the complex‐valued signal constellation to the same finite‐field arithmetic is proposed. The consequences on the factorisation task present in LRA preequalisation are discussed and covered by numerical performance evaluations based on non‐binary low‐density parity‐check codes. [ABSTRACT FROM AUTHOR]