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Reconfigurable hardware is a promising technology for implementing firewalls, routing mechanisms, and new protocols for evolving high-performance network systems. This work presents a novel deterministic approach for a Range-enhanced Reconfigurable Packet Classification Engine based on the number of rules on FPGAs. The proposed framework uses a RAM-established Ternary Match to represent the prefix and the range prefix and efficient rule-reordering for priority selection to get both best-match and multi-match in the same architecture. The recommended framework exhibits 3.2 Mbits of LUT-RAM-based ternary content addressable memory (TCAM) to hold a maximum of 31.3 K of 104- bit rules with 520 MPPS . LUT-RAM, along with BRAM, shows 4 Mbits of TCAM space to implement 38.5 K of 104- bit rules to sustain a throughput of 400 MPPS on Virtex-7 FPGA. The complete architecture offers scalability, better resource utilization (minimum of 50% ), representation of inverse prefix with single entry, range expansion with a single rule, getting best- and multi-match, and determination of the required number of FPGA resources for a particular dataset.

Field Programmable Gate Arrays (FPGAs) are often used in space, military, and commercial applications due to their re-programmable feature. FPGAs are semiconductor components susceptible to soft errors due to radiation effects. Fault tolerance is a critical feature for improving the reliability of electronic and computational components in high-safety applications. Triple Modular Redundancy (TMR) is electronic systems’ most commonly used fault-tolerant technique. TMR is reliable and efficient to recover the single-event upsets. However, the limitation of this technique is the area overhead. Prior work has proposed many conventional fault-tolerant approaches that have been unable to avoid area overhead. This paper introduces a novel work related to an error analysis-based technique. This technique works with an error percentage, and a preferential algorithm, which is also proposed to reduce the hardware complexity in the existing works. This technique can be applied on various types of arithmetic circuits. The proposed technique is applied to the adder circuit to verify the hardware usage, power consumption, and delay; it has been implemented on the Proasic3e 3000 FPGA. The simulated results were observed as 39.89% fewer IO cells, 47.10% fewer core cells, and 5.32% less power as compared to the TMR-based adder.

Decimal converter plays an essential role in decimal arithmetic operations. A decimal converter is used to convert binary partial products to Binary Coded Decimal. Here, the use of the converter ce...

Packet Classification is the enabling function performed in commodity switches for providing various services such as access control, intrusion detection, load balancing, and so on. Ternary Content Addressable Memories (TCAMs) are the de facto standard for performing packet classification at high speeds. However, TCAMs are highly costlier both in terms of cost and power consumption, forcing the switch vendors towards placing lots of effort for power management. Hence, power-efficient solutions for TCAM-based packet classification are highly relevant even today. In this article, we propose a novel rule placement algorithm based on the unique field values’ presence within the rule databases. We evaluate the total search that is needed to be inspected with respect to the traditional placement approach and the proposed placement approach based on the information content within the fields. Simulation results showed an average reduction of 30.55% in the search space by the proposed placement approach, thereby resulting in an average reduction of 18.85% per search energy over TCAM. With typical TCAM clock speeds ranging between 200--400MHz, this reduction in the per-search energy maps to a huge reduction in the total energy consumed by the TCAM-based network switches. The proposed solution is plug-and-play type requiring only minimal pre-processing within the Network Processing Unit (NPU) of the switches and edge routers.

The modern real time applications such as orthogonal frequency division multiplexing, data/image/video compression, speech processing, and etc., demand high performance discrete orthogonal transform designs with lesser area/power and delay. This paper proposes two kinds of architectures to perform multiple N-point 1D-discrete orthogonal transforms on single chip. They are FFT parallel architecture based and matrix-vector multiplier based. The proposed architectures have the feasibility to perform N or $\frac {N}{2}$ or $\frac {N}{4}$ or $\frac {N}{8}$ -point discrete forward/reverse orthogonal transforms, where FFT, discrete Cosine, Sine, Haar, Hartley, Slant, and Walsh-Hadamard transforms are considered. The novelty with proposed architectures is the provision of multiple transforms using the single hardware. The frequency of the proposed 16-point FFT parallel architecture based and matrix-vector multiplier based 1D-discrete orthogonal transform architectures are 110.9 MHz and 26.65 MHz using 45 nm technology respectively.

The speed requirement for the routing table lookup and the packet classification is rapidly increasing due to the increase in the number of packets needed to be processed per second. The hardware-based packet classification relies on ternary content addressable memory (TCAM) to meet this speed requirement. However, TCAM consumes huge power and also supports only for longest prefix match and exact match, where the classification rule also has a range match (RM) field. Hence, it is mandatory to encode the RM into prefix match to accommodate the rule in TCAM. In the worst case, one rule is encoded into (2 W -2) 2 rules (where W is a number of bits to represent range). This work proposes a novel RM architecture, and a detailed analysis about the range field on the standard dataset and the real-life classifier rules are presented. In the literature, the existing RM architecture is used to avoid the range to prefix conversion, but due to the serial operation, it lacks in performance. For constant time lookup, TCAM is the best option, but it does not support RM. The proposed architecture takes one clock cycle for RM and does not require any encoding/ conversion. Hence, there will be a single entry for every rule. It is observed that just 4% of the two-dimensional range rules are present in this dataset, and it will increase the rule set size by 4 times in the best case and nearly 30 times in the worst case. The proposed RM circuit is operated in parallel with TCAM without compromising the speed, and this circuit saves huge power around 70% and area around 61%, where the range to prefix conversion/encoding is completely avoided. The proposed architecture is well suited for current IPv4- and IPv6-based networks, as well as in software-defined networks in the near future.

Many of the applications that are used in the handheld devices are multimedia processing. Multimedia processing will consume huge power due to its computations, as a result battery gets drained quickly. Multimedia applications are error tolerant applications, as human eye can not able to recognize the error present in the multimedia content. Approximate computing is one of the alternative to enhance the battery life. Hadamard transform is used in image coding, CDMA and MPEG, etc,. applications. This paper proposes an approximate hardware architecture for computing discrete Hadamard transform. The proposed approximate Hadamard transform architecture consumes 33% and 31 % lesser area, 22% and 14% lesser delay, power reduces by 36% and 39% compared to the existing exact 16-point and 4-point Hadamard transform. The PSNR values of 4-bit LSB approximate 16-point and 4-point Hadamard transform's output image is 36.30 and 36.32 respectively.

Many of the modern signal/image processing applications use Discrete Fourier Transform (DFT) as one of the core functional elements to process the input signal/image from one domain to another. Hardware design of the DFT is complex and many researchers have proposed variety of methods to implement it. Computational complexity of 1D, N-point DFT is $O(N^{2})$ . Distributed arithmetic is one of the promising and efficient technique to implement any discrete orthogonal transform. This paper proposes an efficient approach to implement DFT using distributed arithmetic. The proposed technique exploits the repetitive pattern of coefficients and stores efficiently in the memory and reduces the storage by 75% compared to the existing group distributed arithmetic for 8-point DFT. The proposed approach uses the property of group distributed arithmetic efficiently in the architecture.

In this work, VLSI architectures with less delay/area for lifting based DWT are proposed.The proposed logic used for area efficient DWT is to perform the whole operation with one processing element.The proposed logic used for delay efficient DWT is to perform the whole operation with multiple processing elements in parallel.In both the cases, the processing element consists of one floating point adder and one proposed fused multiply add design. In this paper, high performance VLSI architectures for lifting based 1D and 2D-Discrete wavelet transforms (DWTs) are proposed. The proposed logic used for area efficient lifting based DWT is to perform the whole operation with one processing element. Similarly, the proposed logic used for delay efficient lifting based DWT is to perform the whole operation with multiple processing elements in parallel. In both the cases, the processing element consists of one floating point adder and one proposed fused multiply add design. The proposed and existing lifting based 1D and 2D lifting based DWTs are implemented with 45źnm technology. The results show that the proposed designs achieve significant improvement compared with existing architectures. For example, 9-point 2-parallel proposed (9, 7) single level 1D-DWT achieves 33.5% of reduction in total cycle delay compared with direct form. Similarly, 9-point single PE proposed (9, 7) single level 1D-DWT achieves 59.8% and 75.5% of reduction in total area and net power over direct form respectively.

The modern real time applications like orthogonal frequency division multiplexing and etc., demand high performance fast Fourier transform (FFT) design with less area and clock cycles. This paper proposes efficient FFT VLSI architectures using folded/parallel implementation. In the proposed folded FFT architecture, the number of cycles required to complete the operation is less than single path delay feedback (SDF)/multi-path delay commutator (MDC) architectures. In the proposed parallel FFT architecture, N-point FFT is implemented by using one N/2-point FFT without much extra hardware. Both the proposed architectures are implemented for radix-2, 22, and 4 using 45 nm technology library. The proposed parallel architecture achieves 56.7% and 40.6% of area reduction as compared with the existing parallel architecture based 16-point radix-2 and radix-22 DIF FFTs respectively. The proposed folded architecture achieves 65.5%, 51.1%, and 35.8% of worst path delay reduction as compared with the existing SDF based 16-point radix-2, radix-22, and radix-4 DIF FFTs respectively.

This paper proposes an effective algorithm to design a larger multiplexer using a tree of smaller multiplexers for a particular user defined library. The proposed algorithm outputs the larger multiplexer into a tree based structure, which gives the scope to pipeline the larger multiplexer as per the requirements of data path design. The experimental result shows that the proposed algorithm gives an efficient multiplexer design with less delay compared to existing algorithms. For example, 48-to-1, 31-to-1 multiplexer designs using the proposed algorithm achieve an improvement of 30.4% and 21.95% in delay compared with designs using 2-to-1 multiplexer tree for 45 nm technology respectively.

This brief proposes an efficient very-large-scale integration architecture for folded configurable infinite-impulse response (IIR) filter design, which is used in modern real-time digital signal processing applications such as loudspeaker equalization. The proposed configurable sixth-order IIR filter is designed with three cascaded second-order IIR filters, and the same is used to perform one sixth-order or three second-order or one fourth-order and one second-order IIR filter operations in parallel, where floating-point multiply–accumulate circuit (MAC) is used to design each second-order IIR filter. The proposed sixth-order IIR filter achieves a 58.4% reduction in energy per operation compared with conventional MAC-based architecture using 45-nm technology.

The modern real time applications related to image processing and etc., demand high performance discrete wavelet transform (DWT). This paper proposes the floating point multiply accumulate circuit (MAC) based 1D/2D-DWT, where the MAC is used to find the outputs of high/low pass FIR filters. The proposed technique is implemented with 45 nm CMOS technology and the results are compared with various existing techniques. The proposed 8 x 8-point floating point 2-levels 2D-DWT achieves 27.6% and 83.7% of reduction in total area and net power respectively as compared with existing DWT [9].

This paper proposes an efficient VLSI architecture for integer discrete cosine transform (integer DCT) that is used in real time high efficiency video coding (HEVC) applications. The proposed N-point 1D-Integer DCT architecture consists of signed configurable carry save adder tree based multiplier unit. So, the depth of the architecture falls within the bounds of O(log2 N). The proposed 1D architecture is used to perform one N-point or multiple N 2 ; N 4 ; :::2-point Integer DCTs in parallel. The proposed 1D architecture is used to design 2D folded and parallel designs. The performance results show that the proposed architecture gives better performance compared with existing architectures using 45 nm CMOS TSMC library. The proposed 3232-point parallel Integer DCT achieves 59:1% of improvement in worst path delay compared with odd-even decomposition [3] based architecture.

This article proposes an effective way of implementing a multiply accumulate circuit (MAC) for high-speed floating point arithmetic operations. The real-world applications related to digital signal processing and the like demand high-performance computation with greater accuracy. In general, digital signals are represented as a sequence of signed/unsigned fixed/floating point numbers. The final result of a MAC operation can be computed by feeding the mantissa of the previous MAC result as one of the partial products to a Wallace tree multiplier or Braun multiplier. Thus, the separate accumulation circuit can be avoided by keeping the circuit depth still within the bounds of the Wallace tree multiplier, namely O ( log 2 n ), or Braun multiplier, namely O ( n ). In this article, three kinds of floating point MACs are proposed. The experimental results show 48.54% of improvement in worst path delay achieved by the proposed floating point MAC using a radix-2 Wallace structure compared with a conventional floating point MAC without a pipeline using a 45nm technology library. The same proposed design gives 39.92% of improvement in worst path delay without a pipeline using a radix-4 Braun structure as compared with a conventional design. In this article, a radix-32 Q 32.32 -format-based floating point MAC is proposed using a Wallace tree/Braun multiplier. Also this article discusses the msb prediction problem and its solution in floating point arithmetic that is not available in modern fused multiply-add designs. The performance results show comparisons between the proposed floating point MAC with various floating point MAC designs for radix-2,-4,-8, and -16. The proposed design has lesser depth than a conventional floating point MAC as well as a lower area requirement than other ways of floating point MAC implementation, both with/without a pipeline.

This paper propose the high precision and hardware efficient CORDIC structure for handheld scientific calculator. This structure will compute the standard transcendental functions. CORDIC structure does not use any calculus method such as rational or polynomial functions. The complete structure realization in hardware can be done based on shift and add operation. This paper propose the detailed analysis about number of CORDIC stages versus angle convergence. A novel technique to reduce the ROM based look up table(LUT) size by using fine and coarse grain methods are proposed. Proposed architecture will compute all basic elementary function like logarithmic, trigonometric and exponential functions.

Content addressable memory is a special type of memory which can do search operation in a single clock cycle. CAM has disadvantages of high power dissipation during the matching operation. Ternary content addressable memory (TCAM) is a special type of memory which is used to search for logic 0, logic 1, logic 'x'. These types of memory are used in routers in order to perform the lookup table function in a single clock cycle. As the use of networks, typified by the Internet, has spread widely in recent years, attention has focused on TCAMs as a key device for increasing the speed of packet forwarding (packet data transfers) by networking equipment by enabling high-speed lookup of destinations, etc., for large volumes of information during packet data transfers. Reversible logic has gained its interest in recent years due to its ultra low power characteristics. Many works have been done to reduce the power consumption in TCAM. This paper deals with a novel design of TCAM cells using reversible logic. The proposed design is optimized in terms of number of garbage outputs and quantum cost. The proposed TCAM cell does the function of the conventional TCAM cell.

Content addressable memory is a special type of memory which can do search operation in a single clock cycle. CAM has disadvantages of high power dissipation during the matching operation. Binary content addressable memory (Bi-CAM) is a special type of memory which is used to search for logic 0, logic 1. These types of memories are used in computer networking devices in order to perform the look up table function in a single clock cycle. Reversible logic has gained its interest in recent years due to its minimum heat dissipation characteristics. Many works have been done to reduce the power consumption in BiCAM. This paper deals with a novel design of BiCAM cells using reversible logic. The design is optimized by reducing the number of garbage outputs and quantum cost. The proposed BiCAM cell does the function of the conventional BiCAM cell.

This paper proposes a novel fixed point multiplier architecture with data level parallelism. That is, the same multiplier hardware is used to perform multiple multiplications on different data paths. Here, we proposed a Wallace tree multiplier to perform more number of multiplications in parallel with fewer extra carry save stages than conventional multiplier. The proposed n-bit Wallace structure is used to perform four (n/2)×(n/2)-bit multiplications, two n×(n/2)-bit multiplications and one n × n-bit multiplication in parallel. The experimental results are showing the comparison between the conventional 32-bit Wallace tree multiplier with proposed 32-bit Wallace tree multiplier. The proposed system is having slightly higher depth than conventional multiplier due to 2 extra carry save stages to incorporate multiple multiplications in parallel, which is not possible in conventional Wallace tree multiplier.

This paper proposes a novel fixed point complex number multiply accumulate circuit, which is used in real time digital signal processing applications. The proposed architecture consists of multiplier-cum-accumulator which can be used as multiplier as well as MAC. Here the previous MAC result is added as one of the partial products of the current multiplication. So the depth of the multiplier-cum-accumulator unit remains same as O(log2 n) in case of Wallace tree multiplier based multiplier-cum-accumulator and O(n) in case of Braun multiplier based multiplier-cum-accumulator. And hence the separate accumulator with depth O(log2 n) can be avoided. The performance results are showing that proposed architecture gives the better performance compared with conventional fixed point complex number MAC. The proposed architecture achieves an improvement factor of 32.4% in Wallace tree and 19.1% in Braun multiplier based fixed point complex number MAC with out pipeline using 45 nm technology library. The same architecture achieves an improvement factor of 14.6% in Wallace tree and 12.2% in Braun multiplier based fixed point complex number MAC with pipeline.

This paper provides a novel multi mode interleaver which satisfies all the modulation schemes used in 802.16e. The proposed model is finite state machine based address generation with efficient use of FPGA memory block for storing the read and write address. In terms of maximum operating frequency finite state machine based address generation performs better as compared to the existing technique. Proposed design supports computation of interleaver address dynamically.

In recent years of development in wireless communication many baseband processors been proposed in various fields in order to propel the demand of high performance, less effective area, this changes according to the need of future developments. This paper presents an efficient processor architecture framework with respect to power consumption and area. The proposed framework can accommodate basic demands of extensive modulation schemes with reconfigurable feature. The framework of this baseband processor state 36% less area compared to normal states of architecture which results in 78% of area efficiency. This defines new ways of low power states and purposefully fulfills the need of performance with average higher throughput over time with less power consumption.