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EUV (extreme ultraviolet) lithography is progressively being inserted in high volume manufacturing of semiconductors to keep up with node shrinkage. However, defectivity remains one big challenge to address in order to be able to exploit its full potential. As in any type of lithographic process, processing failures and in-film particles are contributors that need to be reduced by the optimization of coating and development processes and improved dispense systems. On top of these defects, stochastic failures, due to photon shot noise or non-uniformities in the resist, are another major contribution to the defectivity. To support their mitigation, etch process can be used to avoid their transfer to underlying layers. However, it requires a sufficient resist mask thickness. For line and space patterns, providing more resist budget comes with a trade-off which is the increase of pattern collapse failures, especially with shrinking critical dimensions. Collapse mitigation approaches are therefore very important to enable tight pitches and were explored. Stack engineering and especially optimization of resist under layers will be crucial components to enable patterning and defect reduction of shrinking pitches. Finally, as an alternative to traditional chemically amplified resists, metal containing resists are also promising because of their inherent high etch resistance. Dedicated hardware and processes were developed the use of such materials and prevent metal contamination to other tools during further processing steps. In this report will be presented the latest solutions to further decrease defectivity towards manufacturable levels and provide more process margin to achieve better quality patterning towards the limits of NA 0.33 EUV exposure. Furthermore, technologies to improve CD uniformity and stability, which are required for mass production, will also be reported.

Extreme ultraviolet (EUV) lithography faces major challenges for smaller nodes due to the impact of stochastic and processing failures.1 One of the main challenges for pitch shrink at these nodes is the optimization of the trade-off between break type defects versus bridge type defects as the process window between these defect modes gets smaller.2 In this paper, we examine EUV defect reduction techniques for Chemically Amplified Resist (CAR) and Metal Oxide Resist (MOR) via coater/developer process development combined with optimized etching processes.

Although being progressively introduced to mass production, extreme ultraviolet (EUV) lithography still faces major challenges for 5nm and smaller nodes due to the impact of stochastic and processing failures, resulting in very narrow defect process windows. 1 These failures are strongly linked to critical dimension (CD) variations.2 Therefore, careful control of CD is now directly linked to defect reduction in addition to more conventional in-film particles/developer residues reduction. Photoresist profiles are also believed to be one possible limiting factor and improvements via collapse control or increased resist mask thickness for etch transfer need to be considered. In this paper, most recent understandings regarding defect process window limitations and optimization of processes to further enable narrow pitch EUV lithography will be presented.