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A new sample-and-hold (S&H) architecture is proposed for time-interleaved analog-to-digital converter (ADC). The use of this S&H circuit in front-end of a time-interleaved ADC system eliminates the need for sample-time calibration. Using the techniques of precharging and output capacitor coupling along with a new sampling technique called middle-plate-sampling can mitigate the stringent performance requirements for the opamp and sampling switches, resulting in low power consumption and allowing very high sampling rate. Simulated by HSPICE with a standard BSIM3v3 0.18 [micro]m technology, the S&H achieves 10-12 bits resolution for a 1.6-[V.sub.pp] output at 1-GHz sampling rate. The S&H dissipates 12 mW from a 1.8-V supply. Index Terms--Analog integrated circuits, analog-to-digital circuits (ADCs), CMOS analog integrated circuits, low power analog circuits, pipeline, sample-and-hold (S&H) circuits.