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1. High-Accuracy Inference in Neuromorphic Circuits using Hardware-Aware Training

2. Modeling Transient Negative Capacitance in Steep-Slope FeFETs

3. Modeling of Negative Capacitance of Ferroelectric Capacitors as a Non-Quasi Static Effect

4. A Multi-Bit Neuromorphic Weight Cell using Ferroelectric FETs, suitable for SoC Integration

5. Parasitic Bipolar Leakage in III-V FETs: Impact of Substrate Architecture

7. Modeling Transient Negative Capacitance in Steep-Slope FeFETs

8. A Multi-Bit Neuromorphic Weight Cell Using Ferroelectric FETs, suitable for SoC Integration

9. 1Physics of hole transport in strained silicon MOSFET inversion layers

11. (Invited) Strain Modeling in Advanced MOSFET Devices

12. Strain Modeling in Advanced MOSFET Devices

13. A New Direction for III–V FETs for Mobile CPU Operation Including Burst-Mode: In0.35Ga0.65As Channel

14. A detailed physical model for ion implant induced damage in silicon

15. SoC Logic Compatible Multi-Bit FeMFET Weight Cell for Neuromorphic Applications

16. Ferroelectric Switching Delay as Cause of Negative Capacitance and the Implications to NCFETs

17. On the Validity and Applicability of Models of Negative Capacitance and Implications for MOS Applications

19. Modeling and Simulation of Morphing Wing Aircraft

20. SPICE macromodel of silicon-on-insulator-field-effect-transistor-based biological sensors

21. Modeling of Dynamic Loading of Morphing-Wing Aircraft

22. Modeling of Flight Dynamics of Morphing Wing Aircraft

23. Band-to-Band Tunneling in Ge-Rich SiGe Devices

24. Strain Modeling in Advanced MOSFET Devices

25. The Impact of Crystal Cut Error on the Measured Impurity Profiles Resulting from Ion Implantation

26. Toward energy-optimizing rotary wing MAV formations

27. New cost-effective integration schemes enabling analog and high-voltage design in advanced CMOS SOC technologies

28. Scaling reliability and modeling of ferroelectric capacitors

29. Modeling and Simulation to Study Flight Dynamics of a Morphable Wing Aircraft

30. 45nm low-power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistors

38. Analysis of graphene nanoribbons as a channel material for field-effect transistors

47. A 90-nm Logic Technology Featuring Strained-Silicon.

48. Strain Modeling in Advanced MOSFET Devices

49. A Logic Nanotechnology Featuring Strained-Silicon.

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