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Medium-voltage (MV) cascaded H-bridge converter (MV-CHBC) provides a transformerless connection to MV distribution system applications such as grid-connected battery energy storage systems (G-BESSs). An MV-CHBC consists of multiple series-connected submodules (SMs) forming a wye-connected three-phase topology. The blocking voltage of the utilized power semiconductor modules impacts many converter parameters such as the number of required SMs. Thus, a stepwise design methodology is proposed to select the most suitable high-voltage (HV) module for voltages ranging from 4.16 to 35 kV. Considering that the converter current is constant and independent of the regarded voltage level, 4.16-/2.5-, 13.8-/ 8.5-, 25-/15-, and 35-kV/21-MVA MV-CHBC systems are designed considering HV silicon (Si) IGBT and silicon carbide (SiC) MOSFET power modules rated 1.7 kV up to 10 kV. These designs are evaluated per criteria such as power losses, power density, system complexity, and number of parallel-connected modules. A multiattribute decision-making (MADM) technique is applied to evaluate these designs to select the optimal one according to weights for each criterion. For the 4.16-kV/ 2.5-MVA MV-CHBC system, the 3.3-kV SiC MOSFET-based design is the most suitable one. The 6.5-kV SiC MOSFET-based designs are the optimal ones for the 13.8-/8.5- and 25-kV/15-MVA MV-CHBC systems. For the 35-kV/21-MVA MV-CHBC system, 3.3- and 6.5-kV SiC MOSFET-based designs are the most suitable ones. Experimental results of a 3.3-kV SiC MOSFET-based SM are demonstrated to validate the proposed methodology and MV-CHBC simulations under piecewise linear electrical circuit simulation software (PLECS) environment.

High-voltage (HV) wide bandgap (WBG) silicon carbide (SiC) power modules, capable of higher switching frequencies and thermal stresses than their silicon-based counterparts, are well suited for the next generation of highly efficient power converters for medium-voltage (MV) grid applications. HV SiC power modules allow for simpler two-level HV converter topologies, reducing control and system-level complexity while increasing power density, efficiency, and reliability; furthermore, modular designs are also possible for multilevel converters at 15 kV-class distribution voltages and beyond. Both 10 kV and 6.5 kV SiC MOSFETs are leading candidates for developing multiple MV grid applications. This article presents the design and test of a two-level dc–dc solid-state transformer (SST) based on third-generation 10 kV SiC power modules as a building block for MV power conversion. The converter configuration is based on a three-phase dual-active bridge (TPDAB). An integrated leakage methodology is used to meet the series inductance requirements for maximum power transfer and optimize the transformer volume. Because of the transformer stray capacitances and high dv/dt of the SiC MOSFETs, high-frequency oscillations (HFO) become a significant challenge to avoid unwanted voltage spikes, current resonances, and losses. The HFO amplitudes can be minimized by considering transformer winding arrangements with lower stray capacitances, leading to higher oscillation frequencies. Hence, design considerations and boundaries for the power converter and the high-frequency (HF) transformer are derived and presented. Experiments on a 150 kW TPDAB are conducted to validate the proposed design, yielding efficiencies above 98% at 20, 40, and 100 kW power levels, and demonstrate significant mitigation of HFO issues.

Harmonic compensation employing resonant controllers applied to voltage source inverters (VSIs) generally requires complex techniques or a trial-and-error process to design the controller parameters. This article proposes a closed-form solution for designing digital proportional-resonant controllers applied to three-phase four-leg (TP4L) inverters. The proposal presents a sequential procedure that uses closed-form expressions to establish the harmonic frequencies at which resonant stages must be added to comply with individual voltage harmonic distortion standards. The method eliminates the need for a trial-and-error process and ensures compliance with total harmonic distortion (THD) and individual harmonic distortion limits. The frequencies that require compensation and the gains of the resonant controllers are determined by evaluating the difference that presents the output harmonic impedance of the inverter concerning normalized three-phase harmonic impedance limits defined in this work. Furthermore, this article adopts the harmonic distortion restrictions imposed by the Standard IEC 61000-2-2, allowing the harmonic impedance limits to be defined for the reference nonlinear (RNL) load indicated in IEC 62040-3. Experimental results are presented to validate the proposed design using a 5-kVA four-leg inverter, feeding balanced, unbalanced, linear, and nonlinear loads.

A fully normalized algorithm to implement the optimal triple-phase-shift (TPS) modulation strategy of the dual active bridge (DAB) converter is proposed in this article. The algorithm evaluates three simple expressions that fit the optimal solutions obtained in recent works, which allows the algorithm to be implemented in real-time and valid for the whole operating range. As a result, the converter operates under zero voltage switching (ZVS) conditions and minimizes conduction losses. In addition, the algorithm considers the minimum current required to guarantee the ZVS condition that faces the undesired dead-band of switching devices effect. The proposal achieves a soft transition between any operation region and a fast closed-loop response with no stability concern, presenting robustness under leakage inductance deviation. Finally, the algorithm presented in this article is verified with a 4-kW experimental prototype. Experimental results show that the algorithm proposed can be evaluated with less than 2.8 $\mu \text{s}$ and allows soft transition between any operation region to be achieved. Besides, fast closed-loop changes of 750 $\mu \text{s}$ through all the operating ranges, keeping minimum rms current under ZVS, are shown.