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Wireless communication infrastructure is a key enabling technology for smart cities. This paper investigates a novel technique to enhance the performance of 5G base stations by addressing the compensation of nonlinear distortions caused by radiofrequency power amplifiers. For this purpose, a sequential digital predistortion approach that uses twin nonlinear two-box structure along with reduced sampling rates in the feedback path is proposed to implement a linearization system. Such a system is shown to have a correction bandwidth that exceeds the bandwidth of the feedback path. This is achieved by synthesizing the predistortion function in two successive characterization iterations. Both characterizations use the same hardware, which has a reduced sampling rate in the feedback path. Hence, the proposed predistorter scheme does not require any additional hardware compared to standard schemes. Moreover, coarse delay alignment is performed while identifying the memory polynomial function in order to further reduce the computational complexity of the proposed system. Experimental results using an inverse Class-F power amplifier demonstrate the ability of the proposed predistorter to achieve a correction bandwidth of 100 MHz with a feedback sampling rate as low as 25 MSa/s.

In this paper, a hybrid predistortion architecture that allies the benefits of digital and analog predistortion techniques is investigated. This Hybrid Digital/Analog Predistorter (H-DAPD) uses a low order memory polynomial as a baseband digital predistortion function. To alleviate the complexity of the analog predistorter implementation, an amplitude only predistortion function is adopted. The analog predistortion function is used to perform a coarse linearization of the amplifier. The digital predistortion function is then applied to linearize the system made of the analog predistorter and the power amplifier. The H-DAPD predistortion system is found to be superior to purely analog and to purely digital predistortion systems by combining key advantages present in each of these systems. The robustness of the proposed H-DAPD with respect to the hardware impairments that are typically associated with the implementation of analog predistortion is thoroughly discussed, and shown to be superior to that of conventional hybrid and analog predistortion systems. Experimental validation performed on a commercial power amplifier prototype using 5G new radio (NR) test signals demonstrates the enhanced robustness of the proposed H-DAPD to hardware impairments. It was found that standard compliant adjacent channel leakage ratio is obtained with up to 0.3dB resolution in the analog predistorter’s AM/AM function, and up to 3ns delay misalignment between the input and control signals of the analog predistorter. The proposed system is expected to pave the road for future hybrid predistortion systems.

The feasibility of implementing digital predistortion for next-generation wireless communication is faced with a dilemma due to the ever-increasing demand for faster data rates. This causes the utilized bandwidth to increase significantly, as seen in the 5G NR standard in which bandwidths as high as 400 MHz are utilized. Hence, the development of new predistortion techniques in which the forward and feedback paths operate at lower sampling rates is of utmost importance to realize efficient and practical predistortion solutions. In this work, a novel predistortion technique is presented by which the predistortion is divided between the digital and analog domains. The predistorter is composed of a memoryless AM/AM gain function that is implementable in the analog domain, and a nonlinear model with memory effects in the digital domain to relax the sampling rate requirements on both the forward and feedback paths. Experimental validation was carried out with a 20 MHz and a 40 MHz 5G signal, and the results indicate minimal linearization degradation with a sampling rate reduction of 50% and 30%, respectively. This sampling rate reduction is concurrently applied in the digital-to-analog converter of the forward path and the analog-to-digital converter of the feedback path.

This paper proposes a neural networks predistorter based on the bidirectional long-short-term memory (BiLSTM) structure. The proposed predistorter was trained while ensuring that it captures the full intrinsic behavior of the device under test including its memory effects and nonlinear distortions. For this purpose, the device under test was characterized while operating at peak power level with a test signal that emulates strong memory effects. Extensive experimental validation carried on a commercial Gallium Nitride power amplifier prototype demonstrated the ability of the proposed predistorter to maintain standard compliant adjacent channel leakage ratio over a wide range of operating conditions including operating average power, signal bandwidth, and carriers’ configurations. It has been shown that a digital predistorter (DPD) derived from one single training condition was able to linearize the device under test for 72 different test conditions with signal bandwidths between 10MHz and 40MHz, and an operating power range of 5dB. Furthermore, benchmarking results showed that the BiLSTM DPD is unable to maintain satisfactory performance when trained with a sub-optimal signal which does not emulate the full behavior of the device under test. Moreover, it has been shown that the use of the optimal characterization signal along with a generalized memory polynomial predistorter does not lead to satisfactory performance. Hence, the resilience of the predistorter is obtained by combining the suitable model structure along with the appropriate training approach. Such resilient DPD presents a paradigm shift in predistortion techniques which significantly minimizes the need for update. It is anticipated that this work will pave the road for a new generation of DPDs resilient to a wide range of operating conditions.

This paper proposes a novel predistorter architecture suitable for hybrid baseband/RF implementation. The distortion function is split into a memory polynomial and an AM/AM only look-up table (LUT). The memory polynomial function is to be applied in the baseband digital domain whereas the LUT predistorter is suitable for low complexity implementation in either the baseband digital or the RF analog domains. The proposed model was compared to benchmark models using 20MHz and 40MHz wide 5G test signals, and found to be superior in terms of adjacent channel leakage ratio performance and complexity. Experimental results showed that the model can achieve ACLR levels of better than −50dBC with a relatively low number of coefficients. The proposed model requires around 20% less coefficients than the reverse twin-nonlinear two-box model, and achieves slightly better ACLR while easing the analog implementation of the static nonlinearity predistortion function. Most importantly, the low-complexity hybrid implementation of the proposed model can drastically reduce the speed requirements in the digital to analog converter of the signal transmit path by up to 80% when compared to traditional DPD systems.

In this paper, novel Doherty Power Amplifier (DPA) models are presented. The motivation behind the proposed models is to accurately predict static nonlinearities in the compression regions of the carrier and peaking amplifiers. DPAs suffer from a nonlinearity that originates from the carrier amplifier, and a second more pronounced nonlinearity generated at the full compression region following the turn-on of the peaking amplifier. Moreover, these distortions are often observed at different input power levels depending on whether the AM-AM or the AM-PM characteristic is considered. Therefore, the proposed static model is based on independent modeling of the memoryless gain in the polar domain. The static model of the memoryless AM-AM and AM-PM characteristics is augmented with either memory polynomials or deep neural network functions for memory effects modeling. The methodology of building the proposed models and the achieved results are discussed in this paper. The MP based proposed model achieves an NMSE as low as -45.3dB with only 78 model parameters, while the DNN based model achieves an NMSE as low as -46.1dB with only 156 model parameters. However, the DNN based model achieves the best model resilience to changes in the identification data.

A new look-up table based behavioral model for dynamic nonlinear power amplifiers is proposed. This model labelled as hybrid look-up tables model is based on the combination of a memoryless look-up table sub-model and a nested look-up tables one. It is demonstrated that the proposed model circumvents the computational complexity associated with the parameters identification in analytically defined behavioral models. Moreover, the proposed model reduces the size of the standalone nested look-up tables model by approximately 80% while maintaining its accuracy. Furthermore, a novel slew-rate based trimming and indexing technique to reduce the nested look-up tables model size is developed and corroborated experimentally. Additionally, the two-box structure of the hybrid look-up tables model makes it suitable for bandwidth scalability. Experimental validation using LTE-advanced test signals with up to 120MHz bandwidth demonstrates the ability of the proposed hybrid look-up tables model to be bandwidth scalable with less than 0.5dB degradation in the normalized mean-squared error.

A novel class of behavioral models is proposed for LTE-driven Doherty power amplifiers with strong memory effects. The proposed models, labeled augmented twin-nonlinear two-box models, are built by cascading a highly nonlinear memoryless function with a mildly nonlinear memory polynomial with cross terms. Experimental validation on gallium nitride based Doherty power amplifiers illustrates the accuracy enhancement and complexity reduction achieved by the proposed models. When strong memory effects are observed, the augmented twin-nonlinear two-box models can improve the normalized mean square error by up to 3 dB for the same number of coefficients when compared to state-of-the-art twin-nonlinear two-box models. Furthermore, the augmented twin-nonlinear two-box models lead to the same performance as previously reported twin-nonlinear two-box models while requiring up to 80% less coefficients.