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The study has proposed a SODEL FET structure with new channel and S/D profile engineering schemes, fabricated by a selective Si epitaxal growth technique. The advantages of PD-SOI CMOS are reproduced in this bulk substrate-based SODEL FET without having the disadvantages in PD-SOI CMOS. The study stated that SODEL FET would provide a potential solution for high-speed and low-power SoC applications in 90-nm-node bulk CMOS generations and beyond.

A low-resistivity poly-metal gate structure W/WSiN/poly-Si shows thermal stability even after annealing and also achieves a sheet resistivity as low as 1.5 ohm. Annealing gives rise to a uniform WSiN layer between the W and poly-Si in addition to the removal of the WN(sub x) layer. Rutherford backscattering spectrometry shows no silicidation, and an equivalent circuit simulation reveals the negligible effect of the contact resistivity of W and poly-Si on the gate RC delay time. The W/WSiN/poly-Si gate structure may prove extremely useful in sub-quarter-micron MOSFET's.

High substrate current reduction was essential for fully gate overlapped (FOLD) structure optimization of highly reliable deep submicrometer n-channel MOSFET. The optimized FOLD structure decreased parasitic resistance and exhibited high performance at 3.3 Volts operation. The high controllability of the gate electrode in the n-extension region reduced the parasitic effect.