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Enhanced particle removal processes in wet cleaning of semiconductor wafers can cause significant lateral forces on surface structures. These forces have to be limited to below the stability of the (nano) structures on the surface to prevent damage. A mechanical fracture test based on atomic force microscope manipulation was used in liquid media (deionized water, isopropanol, and propylene carbonate) to measure the lateral stability of polysilicon line structures. The results are compared to previously reported results in air. All liquid media investigated here showed a stabilizing effect. Maximum stability was found for immersion in isopropanol. The size of the damage generated was mainly influenced by the viscosity of the liquids. The results do not support a stress corrosion cracking process.

As the dimensions of the structures of integrated circuits shrink, the influence of particles on device yield becomes increasingly important. According to the cleaning requirements of the International Technology Roadmap for Semiconductors (ITRS) in 2007, particles of 32 nm and larger are believed to be detrimental to devices and thus have to be removed. To remove nano-particles with minimal substrate loss and no damage requires very dilute chemistries and sufficiently gentle physical forces in a cleaning process. In this work the performance of an aerosol spray based cleaning technique is evaluated with regard to the removal efficiency of nano-particles as well as substrate loss and structural damage.

The measured lateral stability of polysilicon line structures on a Silicon Oxy-Nitride layer is presented. This has been measured by Lateral Force Microscopy (LFM) in order to understand how much force can be applied to the structure during a wet cleaning process with subsequent drying. The measured values in the lateral dimension are between 2 and 5 uN which is in the same range as expected by mechanical calculations. SEM micrographs of the damaged sites confirm a round breaking shape. The length of the broken line is around 0.5 to 1 um with a lower limit of 0.5 um which is similar to previously reported results on real damage produced by cleaning processes supported with Megasonic energy. The rupture in the AFM experiments occurs clearly in the polysilicon and not at the interfaces of the structure.

With the implementation of Cu and low-k dielectrics in back-end-of-line (BEOL), issues arise in every process step that must be addressed. One of the challenges is the susceptibility of low-k materials to attack during residue removal (polymer) after low-k etch and resist strip. This work focuses on the influence of the plasma etch and ash processes on compatibility of porous low-k dielectrics with a selection of wet chemistries that are used for BEOL polymer removal. The low-k material investigated was porous nanoclustered silica. For blanket films, it is shown that the chemical and structural changes to ultra low-k(ULK) by the plasma treatments are the main contributors to the plasma damage. Two wet chemistries including dHF are found to be compatible with most plasma treatments used in this study. It is also demonstrated that chemistry selection for wet cleaning is linked with the plasma treatments used for etch and ash.

Ni(alloy) silicides have recently gained much attention due to their improved properties. Ni(Pt)Si has indeed become one of most promising candidates to replace NiSi as contact electrodes. To avoid bridging at the spacers and the isolation areas, after self-aligned silicidation (salicidation), un-reacted NiPt needs to be removed. This post salicidation clean process has to be selective towards all possibly exposed materials such as Si3N4 (spacers), SiO2 (field oxide), NiPtSi (contact and gate electrodes), and NiPtSiGe (contact electrodes of source/drain for strain applications). In this work, it is found that dilute HCl/HNO3 mixtures can well be used for NiPt post salicidation clean. It is shown that this process has a high etch rate for NiPt and a high selectivity towards other possibly exposed materials. Furthermore, the sheet resistance and the thickness of the silicides after this selective etch are well within specification providing a clean, environmentally-friendly process with low cost-of-ownership.

Focuses on advanced pre-assembly methods required in smart card assembly. Wafer thinning process; Detaping and dicing; Assembly; Emerging interconnect technologies; Handling thin dice; Packaging the die in the card in a cost-effective manner. INSET: At a Glance.