5 results on '"POOSL"'
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2. HW/SW Design Space Exploration on the Production Cell Setup
- Subjects
gCSP ,Motion Control ,Mechatronics ,METIS-264012 ,IR-68286 ,Handel-C ,CSP ,20-sim ,Real-time FPGA ,QNX ,EWI-16037 ,POOSL ,Embedded Systems ,Ptolemy II - Abstract
This paper describes and compares five CSP based and two CSP related process-oriented motion control system implementations that are made for our Production Cell demonstration setup. Five implementations are software-based and two are FPGA hardware-based. All implementations were originally made with different purposes and investigating different areas of the design space for embedded control software resulting in an interesting comparison between approaches, tools and software and hardware implementations. Common for all implementations is the usage of a model-driven design method, a communicating process structure, the combination of discrete event and continuous time and that real-time behaviour is essential. This paper shows that many small decisions made during the design of all these embedded control software implementations influence our route through the design space for the same setup, resulting in seven different solutions with different key properties. None of the implementations is perfect, but they give us valuable information for future improvements of our design methods and tools.
- Published
- 2009
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3. Execution time analysis of audio algorithms
- Author
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Gopalakrishna, N. (author) and Gopalakrishna, N. (author)
- Abstract
Execution time analysis forms an important part of design space and hardware architectural exploration for hard real-time systems. Some approaches for execution time analysis require prerequisite knowledge of synchronous data flows or timed automata employed in model checkers. This is unsuitable for industry-level use as easy approaches without any prerequisite knowledge requirements are preferred by them. Most of the existing proposals addressing execution time analysis target 'fast' approaches rather than timing accuracy. Also, these existing proposals are validated with simple processors as majority of processors used for hard real-time embedded software are not so complex. However, for audio applications employing audio algorithms, modern processors with high performance are required, to be scalable with increasing audio algorithm complexity. Execution time analysis of audio algorithms on these modern processors is gaining importance as sampling frequencies are getting higher and deadlines getting shorter. In this thesis, we propose an industry acceptable model/simulation framework to perform execution time analysis of audio algorithms on modern mono core and multi-core processors (operating in asymmetric multiprocessing mode). Our framework combines open-source tools such as Gcov, POOSL modelling language (Parallel object-oriented specification language) and Gem5 which is a computer architecture simulator to determine WCET of an audio algorithm using dynamic means as static WCET techniques lead to huge overestimations. This solution framework was proposed after conducting experiments targeting execution time analysis at different abstraction levels and evaluating results based on accuracy, flexibility, hardware compatibility and scalability. Our proposed technique is flexible as Gem5 models several processor architectures and expressing audio algorithms at the basic block abstraction level allows parameters such as loop bounds to be changed easily. It can be ea, Embedded Systems, Microelectronics & Computer Engineering, Electrical Engineering, Mathematics and Computer Science
- Published
- 2014
4. From POOSL to UPPAAL : transformation and quantitative analysis
- Author
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Xing, Jiansheng, Theelen, B.D., Langerak, Rom, van de Pol, Jaco, Tretmans, Jan, Voeten, J.P.M., Gomes, L., Khomenko, V., Fernandes, J.M., and Electronic Systems
- Subjects
Model checking ,Modeling language ,Design space exploration ,Computer science ,Performance ,Real-time computing ,02 engineering and technology ,Transformation ,EC Grant Agreement nr.: FP7/214755 ,CR-B.2.2 ,0202 electrical engineering, electronic engineering, information engineering ,POOSL ,Quantitative analysis ,FMT-FMPA: FORMAL METHODS FOR PERFORMANCE ANALYSIS ,RapidIO ,Network packet ,Verification ,020207 software engineering ,Specification language ,Motion control ,Automaton ,UPPAAL ,Computer engineering ,CR-B.8 ,020201 artificial intelligence & image processing ,EC Grant Agreement nr.: FP7-ICT-2007-1 - Abstract
POOSL (Parallel Object-Oriented Specification Language) is a powerful general purpose system-level modeling language. In research on design space exploration of motion control systems, POOSL has been used to construct models for performance analysis. The considered motion control algorithms are characterized by periodic execution. They are executed by multiple processors, which are interconnected by Rapid Input/Output (RapidIO) packet switches. Packet latencies as worst-case latencies and average-case latencies are essential performance criteria for motion control systems. However, POOSL analysis merely allows for estimation results for these latency metrics since it is primarily based on simulation. Because motion control systems are time-critical and safety-critical, worst-case latencies of packets are strict timing constraints. Therefore exact worst-case latencies are to be determined. Motivated by this requirement we propose to use model checking techniques. In this paper we illustrate how a POOSL model of a (simplified) motion control system can be transformed into an UPPAAL model and we verify its functional behavior and worst-case latencies. Moreover, we show that analysis of average-case latencies can also be accomplished with assistance of the model checking tool UPPAAL.
- Published
- 2010
5. HW/SW Design Space Exploration on the Production Cell Setup
- Author
-
Groothuis, M.A., Welch, P.H., Roebbers, H., Broenink, Johannes F., and Barnes, F.R.M.
- Subjects
gCSP ,Motion Control ,Mechatronics ,METIS-264012 ,IR-68286 ,Handel-C ,CSP ,20-sim ,Real-time FPGA ,QNX ,EWI-16037 ,POOSL ,Embedded Systems ,Ptolemy II - Abstract
This paper describes and compares five CSP based and two CSP related process-oriented motion control system implementations that are made for our Production Cell demonstration setup. Five implementations are software-based and two are FPGA hardware-based. All implementations were originally made with different purposes and investigating different areas of the design space for embedded control software resulting in an interesting comparison between approaches, tools and software and hardware implementations. Common for all implementations is the usage of a model-driven design method, a communicating process structure, the combination of discrete event and continuous time and that real-time behaviour is essential. This paper shows that many small decisions made during the design of all these embedded control software implementations influence our route through the design space for the same setup, resulting in seven different solutions with different key properties. None of the implementations is perfect, but they give us valuable information for future improvements of our design methods and tools.
- Published
- 2009
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