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14 results on '"Packet Parsing"'

1. The design of a configurable and low-latency packet parsing system for communication networks.

Author

Hsu, Kai-Sheng and Shen, Chung-An

Subjects
TELECOMMUNICATION systems, ARCHITECTURAL design, INTERNET protocol version 6, PARSING (Computer grammar), VERY large scale circuit integration
Abstract

Parsing is a critical packet processing function in the network node, and the performance and configurability of the packet parsing is essential for designing a low-latency and highly flexible network. This paper presents the VLSI architecture design and circuit implementation of a configurable and low-latency packet parser. The proposed packet parser is based on an instruction architecture to achieve configurability. Furthermore, a novel instruction-reusing scheme is employed in the packet parser so that the instruction-fetch operation is minimized and the latency is reduced. Moreover, in order to reduce size of the required memory, a new structure for the instruction memory is designed where multiple instructions share the same memory location. The proposed packet parser is designed and implemented with a ASIC design flow as well as based on the FPGA platform. Performance evaluations based on the post-layout simulation shows that the proposed packet parser reduces the latency by 30% and the required memory by 70%for the IPv4 and IPv6 protocols. [ABSTRACT FROM AUTHOR]

Published
2023
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2. Deep packet inspection oriented high speed packet parsing architecture

Author

Yong-ji DONG, Yun-fei GUO, Wan-wei HUANG, and Hui-qun HUANG

Subjects
packet parsing, deep packet inspection, binary trie, network security, reconfiguration, NetFPGA, Telecommunication, TK5101-6720
Abstract

A deep packet inspection oriented high speed packet parsing architecture called BiPPCS (bidirectional packet parsing architecture for content security) was proposed. Firstly, the content extraction tree was used to describe the cou-pling of the protocol relationship to improve flexibility of the packet parsing. Secondly, hardware bi-directional parallel pipeline was used to enhance the processing rate of the packet parsing. Thirdly, a node mapping algorithm was used to balance the number of nodes on all pipeline stages to optimize the storage space. Analysis and simulation show that BiPPCS gets balance among the rate processing, resource consumption and other aspects.

Published
2013
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3. A custom processor for protocol-independent packet parsing

Author

Hesam Zolfaghari, Davide Rossi, Jari Nurmi, Zolfaghari H., Rossi D., Nurmi J., Tampere University, Electrical Engineering, and Research area: Computer engineering

Subjects
Advanced program control, Parsing, Computer Networks and Communications, Computer science, Network packet, business.industry, 213 Electronic, automation and communications engineering, electronics, Packet processing, Throughput, computer.software_genre, Networking hardware, Packet parsing, Software defined networking, Artificial Intelligence, Hardware and Architecture, Programmable data plane, State (computer science), Communications protocol, business, Software-defined networking, computer, Software, Computer network
Abstract

Networking devices such as switches and routers have traditionally had fixed functionality. They have the logic for the union of network protocols matching the application and market segment for which they have been designed. Possibility of adding new functionality is limited. One of the aims of Software Defined Networking is to make packet processing devices programmable. This provides for innovation and rapid deployment of novel networking protocols. The first step in processing of packets is packet parsing. In this paper, we present a custom processor for packet parsing. The parser is protocol-independent and can be programmed to parse any sequence of headers. It does so without the use of a Ternary Content Addressable Memory. As a result, the area and power consumption are noticeably smaller than in the state of the art. Moreover, its output is the same as that of the parser used in the Reconfigurable Match Tables (RMT). With an area no more than that of parsers in the RMT architecture, it sustains aggregate throughput of 3.4 Tbps in the worst case which is an improvement by a factor of 5. acceptedVersion

Published
2020

4. Low-latency Packet Parsing in Software Defined Networks

Author

Davide Rossi, Jari Nurmi, Hesam Zolfaghari, Tampere University, Electronics and Communications Engineering, Research group: Wireless Communications and Positioning, Research group: System-on-Chip for GNSS, Wireless Communications and Cyber-Physical Embedded Computing, Zolfaghari H., Rossi D., and Nurmi J.

Subjects
Ethernet, Parsing, Software Defined Networking, Network packet, computer.internet_protocol, Computer science, business.industry, 213 Electronic, automation and communications engineering, electronics, ComputerSystemsOrganization_COMPUTER-COMMUNICATIONNETWORKS, 020208 electrical & electronic engineering, Packet Parsing, Throughput, 02 engineering and technology, computer.software_genre, IPv4, 020202 computer hardware & architecture, IPv6, Programmable data plane, Header, 0202 electrical engineering, electronic engineering, information engineering, Advanced Program Control, Latency (engineering), business, computer, Computer network
Abstract

Packet parsing is the first step in processing of packets in devices such as switches and routers. In this paper, we present a totally new program control unit as well as further enhancements for a recently designed packet parser architecture which can parse headers of most commonly used protocols such as Ethernet, IPv4, IPv6 and TCP in a time window shorter than 10 nanoseconds. However, when it comes to parsing variable-length headers and multiple stacked headers, it deviates from its maximum throughput due to inefficiencies in its program control logic. We have designed and employed a more advanced program control logic that improves parsing time of variable length headers such as IPv4 header by up to 48 percent and parsing time of typical header stacks used on the Internet by 16 to 21.42 percent. Our solution can sustain aggregate throughput of 640 Gbps while requiring only 30 percent of the number of gates used in the parser used in the Reconfigurable Match Tables architecture. acceptedVersion

Published
2018

5. An Explicitly Parallel Architecture for Packet Parsing in Software Defined Networks

Author

Jari Nurmi, Hesam Zolfaghari, Davide Rossi, Tampere University, Electronics and Communications Engineering, Doctoral Programme in Computing and Electrical Engineering, Research group: System-on-Chip for GNSS, Wireless Communications and Cyber-Physical Embedded Computing, Research group: Wireless Communications and Positioning, Zolfaghari, Hesam, Rossi, Davide, and Nurmi, Jari

Subjects
business.product_category, Software Defined Networking, Computer Networks and Communications, Computer science, Packet Parsing, Throughput, 02 engineering and technology, computer.software_genre, Factor (programming language), 0202 electrical engineering, electronic engineering, information engineering, Protocol (object-oriented programming), computer.programming_language, Parsing, Network packet, 213 Electronic, automation and communications engineering, electronics, 020208 electrical & electronic engineering, ComputerSystemsOrganization_COMPUTER-COMMUNICATIONNETWORKS, Explicit Parallelism, 020202 computer hardware & architecture, TheoryofComputation_MATHEMATICALLOGICANDFORMALLANGUAGES, Computer architecture, Hardware and Architecture, Very long instruction word, Packet Processing Pipeline, Network switch, Software-defined networking, business, computer, Very Long Instruction Word
Abstract

Packet parsing is the first step in processing of packets in devices such as network switches and routers. The process of packet parsing has become more challenging due to the increase in line rates and emergence of Software Defined Networking which leads to new protocols being adopted. In this paper, we present a novel architecture for parsing of packets. The architecture is fully programmable and is not tied to any specific protocol. It can be programmed to parse any protocol making it suitable for Software Defined Networks. Compared with the parser used in the Reconfigurable Match Tables, our parser improves supported throughput by a factor of 3.2. Moreover, to achieve the target throughput of 640 Gbps, our parser needs only 2 percent of the number of gates used in the parsers of Reconfigurable Match Tables. acceptedVersion

Published
2018

6. Taking Control of SDN-based Cloud Systems via the Data Plane

Author

Anja Feldmann, Tobias Fiebig, Felicitas Hetzelt, Kashyap Thimmaraju, Stefan Schmid, Jean-Pierre Seifert, and Bhargava Shastry

Subjects
Network isolation, Virtual switches, Computer science, MPLS, Distributed computing, Network virtualization, Cloud computing, 02 engineering and technology, Fast path, computer.software_genre, SDN, NFV, Server, 0202 electrical engineering, electronic engineering, information engineering, Data plane security, Cloud computing security, Open vSwitch, business.industry, 020206 networking & telecommunications, Attack surface, ROP, Packet parsing, OpenStack, Virtual machine, Cloud security, Threat model, 020201 artificial intelligence & image processing, Attacker models, business, computer
Abstract

Virtual switches are a crucial component of SDN-based cloud systems, enabling the interconnection of virtual machines in a flexible and "software-defined" manner. This paper raises the alarm on the security implications of virtual switches. In particular,we showthat virtual switches not only increase the attack surface of the cloud, but virtual switch vulnerabilities can also lead to attacks of much higher impact compared to traditional switches. We present a systematic security analysis and identify four design decisions which introduce vulnerabilities. Our findings motivate us to revisit existing threat models for SDNbased cloud setups, and introduce a new attacker model for SDN-based cloud systems using virtual switches. We demonstrate the practical relevance of our analysis using a case study with Open vSwitch and OpenStack. Employing a fuzzing methodology, we find several exploitable vulnerabilities in Open vSwitch. Using just one vulnerability we were able to create a worm that can compromise hundreds of servers in a matter of minutes. Our findings are applicable beyond virtual switches: NFV and high-performance fast path implementations face similar issues. This paper also studies various mitigation techniques and discusses how to redesign virtual switches for their integration.

Published
2018

7. The vAMP Attack:Taking control of cloud systems via the unified packet parser

Author

Anja Feldmann, Felicitas Hetzelt, Stefan Schmid, Kashyap Thimmaraju, Bhargava Shastry, Tobias Fiebig, and Jean-Pierre Seifert

Subjects
Data Plane Security, computer.internet_protocol, Computer science, MPLS, 0211 other engineering and technologies, Packet Parsing, Network virtualization, Cloud computing, Multiprotocol Label Switching, 02 engineering and technology, computer.software_genre, Cloud Security, SDN, Network Virtualization, NFV, 020204 information systems, Header, 0202 electrical engineering, electronic engineering, information engineering, 021110 strategic, defence & security studies, Cloud computing security, Network packet, business.industry, Open vSwitch, Virtualization, ROP, OpenStack, Virtual machine, Attacker Models, Network Isolation, business, computer, Computer network, Virtual Switches
Abstract

Virtual switches are a crucial component of cloud operating systems that interconnect virtual machines in a flexible manner. They implement complex network protocol parsing in the unified packet parser-parsing all supported packet header fields in a single pass- and are commonly co-located with the virtualization layer. We find that this significantly reduces the barrier for low-budget attackers to launch high impact attacks in the cloud. This leads us to introduce the virtual switch attacker model for packet-parsing, in short the vAMP attack. Using OpenStack, a cloud operating system, and Open vSwitch, a virtual switch, we demonstrate how current virtual switch designs cannot withstand vAMP. Thereby giving a weak attacker full control of the cloud in a matter of minutes.

Published
2017

8. A custom processor for protocol-independent packet parsing.

Author

Zolfaghari, Hesam, Rossi, Davide, and Nurmi, Jari

Subjects
*SOFTWARE-defined networking, *PARSING (Computer grammar), *COMPUTER network protocols, *SWITCHING systems (Telecommunication), *ARCHITECTURE
Abstract

Networking devices such as switches and routers have traditionally had fixed functionality. They have the logic for the union of network protocols matching the application and market segment for which they have been designed. Possibility of adding new functionality is limited. One of the aims of Software Defined Networking is to make packet processing devices programmable. This provides for innovation and rapid deployment of novel networking protocols. The first step in processing of packets is packet parsing. In this paper, we present a custom processor for packet parsing. The parser is protocol-independent and can be programmed to parse any sequence of headers. It does so without the use of a Ternary Content Addressable Memory. As a result, the area and power consumption are noticeably smaller than in the state of the art. Moreover, its output is the same as that of the parser used in the Reconfigurable Match Tables (RMT). With an area no more than that of parsers in the RMT architecture, it sustains aggregate throughput of 3.4 Tbps in the worst case which is an improvement by a factor of 5. [ABSTRACT FROM AUTHOR]

Published
2020
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9. Analýza a extrakce položek z hlaviček paketů v FPGA

Author

Kořenek, Jan, Košař, Vlastimil, Kořenek, Jan, and Košař, Vlastimil

Abstract

Zariadenia, ktoré sa zúčastňujú komunikácie prostredníctvom počítačových sietí, potrebujú spracovávať pakety a získavať informácie z hlavičiek protokolov. S nárastom počtu protokolov a častými zmienami v ich definíciách, vzniká potreba zaistiť nielen vysokú rýchlosť, ale aj flexibilitu analyzátorov paketov. Preto je cieľom tejto práce vytvoriť návrh jednotky, ktorá umožní jednoducho definovať nové protokoly a generovať výkonnú hardwarovú architektúru. Využitie jazyka P4, popisujúceho hlavičky prokolov a spracovávanie paketov, v kombinácii s možnosťou rekonfigurovať hradlové polia FPGA, nám umožňuje vytvoriť flexibilný analyzátor paketov. Aby bolo možné dostatočne rýchlo premietať zmeny v popise tohto analyzátora, bol vyvynutý program mapujúci popis v jazyku P4 do navrhnutej architektúry., Network devices need to process packets and gather information from header fields. Packet parsers become outdated due to increasing number of protocols and frequent changes in their definitions. This thesis aims to create design of flexible and powerful packet parser. P4 language was designed to define packet processing. Flexible parsers can be constructed by combining potential of P4 with reconfigurable FPGA technology. Program mapping P4 language to designed architecture was implemented in order to promptly reflect changes in parser model.

10. Analýza a extrakce položek z hlaviček paketů v FPGA

Author

Kořenek, Jan, Košař, Vlastimil, Kořenek, Jan, and Košař, Vlastimil

Abstract

Zariadenia, ktoré sa zúčastňujú komunikácie prostredníctvom počítačových sietí, potrebujú spracovávať pakety a získavať informácie z hlavičiek protokolov. S nárastom počtu protokolov a častými zmienami v ich definíciách, vzniká potreba zaistiť nielen vysokú rýchlosť, ale aj flexibilitu analyzátorov paketov. Preto je cieľom tejto práce vytvoriť návrh jednotky, ktorá umožní jednoducho definovať nové protokoly a generovať výkonnú hardwarovú architektúru. Využitie jazyka P4, popisujúceho hlavičky prokolov a spracovávanie paketov, v kombinácii s možnosťou rekonfigurovať hradlové polia FPGA, nám umožňuje vytvoriť flexibilný analyzátor paketov. Aby bolo možné dostatočne rýchlo premietať zmeny v popise tohto analyzátora, bol vyvynutý program mapujúci popis v jazyku P4 do navrhnutej architektúry., Network devices need to process packets and gather information from header fields. Packet parsers become outdated due to increasing number of protocols and frequent changes in their definitions. This thesis aims to create design of flexible and powerful packet parser. P4 language was designed to define packet processing. Flexible parsers can be constructed by combining potential of P4 with reconfigurable FPGA technology. Program mapping P4 language to designed architecture was implemented in order to promptly reflect changes in parser model.

11. Analýza a extrakce položek z hlaviček paketů v FPGA

Author

Kořenek, Jan, Košař, Vlastimil, Kořenek, Jan, and Košař, Vlastimil

Abstract

Zariadenia, ktoré sa zúčastňujú komunikácie prostredníctvom počítačových sietí, potrebujú spracovávať pakety a získavať informácie z hlavičiek protokolov. S nárastom počtu protokolov a častými zmienami v ich definíciách, vzniká potreba zaistiť nielen vysokú rýchlosť, ale aj flexibilitu analyzátorov paketov. Preto je cieľom tejto práce vytvoriť návrh jednotky, ktorá umožní jednoducho definovať nové protokoly a generovať výkonnú hardwarovú architektúru. Využitie jazyka P4, popisujúceho hlavičky prokolov a spracovávanie paketov, v kombinácii s možnosťou rekonfigurovať hradlové polia FPGA, nám umožňuje vytvoriť flexibilný analyzátor paketov. Aby bolo možné dostatočne rýchlo premietať zmeny v popise tohto analyzátora, bol vyvynutý program mapujúci popis v jazyku P4 do navrhnutej architektúry., Network devices need to process packets and gather information from header fields. Packet parsers become outdated due to increasing number of protocols and frequent changes in their definitions. This thesis aims to create design of flexible and powerful packet parser. P4 language was designed to define packet processing. Flexible parsers can be constructed by combining potential of P4 with reconfigurable FPGA technology. Program mapping P4 language to designed architecture was implemented in order to promptly reflect changes in parser model.

12. Analýza a extrakce položek z hlaviček paketů v FPGA

Author

Kořenek, Jan, Košař, Vlastimil, Kořenek, Jan, and Košař, Vlastimil

Abstract

Zariadenia, ktoré sa zúčastňujú komunikácie prostredníctvom počítačových sietí, potrebujú spracovávať pakety a získavať informácie z hlavičiek protokolov. S nárastom počtu protokolov a častými zmienami v ich definíciách, vzniká potreba zaistiť nielen vysokú rýchlosť, ale aj flexibilitu analyzátorov paketov. Preto je cieľom tejto práce vytvoriť návrh jednotky, ktorá umožní jednoducho definovať nové protokoly a generovať výkonnú hardwarovú architektúru. Využitie jazyka P4, popisujúceho hlavičky prokolov a spracovávanie paketov, v kombinácii s možnosťou rekonfigurovať hradlové polia FPGA, nám umožňuje vytvoriť flexibilný analyzátor paketov. Aby bolo možné dostatočne rýchlo premietať zmeny v popise tohto analyzátora, bol vyvynutý program mapujúci popis v jazyku P4 do navrhnutej architektúry., Network devices need to process packets and gather information from header fields. Packet parsers become outdated due to increasing number of protocols and frequent changes in their definitions. This thesis aims to create design of flexible and powerful packet parser. P4 language was designed to define packet processing. Flexible parsers can be constructed by combining potential of P4 with reconfigurable FPGA technology. Program mapping P4 language to designed architecture was implemented in order to promptly reflect changes in parser model.

13. Analýza a extrakce položek z hlaviček paketů v FPGA

Author

Kořenek, Jan, Košař, Vlastimil, Selecký, Roman, Kořenek, Jan, Košař, Vlastimil, and Selecký, Roman

Abstract

Zariadenia, ktoré sa zúčastňujú komunikácie prostredníctvom počítačových sietí, potrebujú spracovávať pakety a získavať informácie z hlavičiek protokolov. S nárastom počtu protokolov a častými zmienami v ich definíciách, vzniká potreba zaistiť nielen vysokú rýchlosť, ale aj flexibilitu analyzátorov paketov. Preto je cieľom tejto práce vytvoriť návrh jednotky, ktorá umožní jednoducho definovať nové protokoly a generovať výkonnú hardwarovú architektúru. Využitie jazyka P4, popisujúceho hlavičky prokolov a spracovávanie paketov, v kombinácii s možnosťou rekonfigurovať hradlové polia FPGA, nám umožňuje vytvoriť flexibilný analyzátor paketov. Aby bolo možné dostatočne rýchlo premietať zmeny v popise tohto analyzátora, bol vyvynutý program mapujúci popis v jazyku P4 do navrhnutej architektúry., Network devices need to process packets and gather information from header fields. Packet parsers become outdated due to increasing number of protocols and frequent changes in their definitions. This thesis aims to create design of flexible and powerful packet parser. P4 language was designed to define packet processing. Flexible parsers can be constructed by combining potential of P4 with reconfigurable FPGA technology. Program mapping P4 language to designed architecture was implemented in order to promptly reflect changes in parser model.

14. Analýza a extrakce položek z hlaviček paketů v FPGA

Author

Kořenek, Jan, Košař, Vlastimil, Selecký, Roman, Kořenek, Jan, Košař, Vlastimil, and Selecký, Roman

Abstract

Zariadenia, ktoré sa zúčastňujú komunikácie prostredníctvom počítačových sietí, potrebujú spracovávať pakety a získavať informácie z hlavičiek protokolov. S nárastom počtu protokolov a častými zmienami v ich definíciách, vzniká potreba zaistiť nielen vysokú rýchlosť, ale aj flexibilitu analyzátorov paketov. Preto je cieľom tejto práce vytvoriť návrh jednotky, ktorá umožní jednoducho definovať nové protokoly a generovať výkonnú hardwarovú architektúru. Využitie jazyka P4, popisujúceho hlavičky prokolov a spracovávanie paketov, v kombinácii s možnosťou rekonfigurovať hradlové polia FPGA, nám umožňuje vytvoriť flexibilný analyzátor paketov. Aby bolo možné dostatočne rýchlo premietať zmeny v popise tohto analyzátora, bol vyvynutý program mapujúci popis v jazyku P4 do navrhnutej architektúry., Network devices need to process packets and gather information from header fields. Packet parsers become outdated due to increasing number of protocols and frequent changes in their definitions. This thesis aims to create design of flexible and powerful packet parser. P4 language was designed to define packet processing. Flexible parsers can be constructed by combining potential of P4 with reconfigurable FPGA technology. Program mapping P4 language to designed architecture was implemented in order to promptly reflect changes in parser model.

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