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In this work, the effect of channel length on the performance of an N-channel Nano-sheet Transistor (NST) for analog circuits has been investigated. A fully-calibrated TCAD platform is used to evaluate the performance of NST devices with channel lengths ranging from 10 nm to 240 nm. The maximum transconductance measured is 0.65 mS for gate length of 24 nm. In addition, the transconductance efficiency ranging from 3 V−1 to 38 V−1 is observed. Intrinsic gain increases from 7.3 to 121.65 as the gate length is varied from 10 nm to 240 nm. For 12 nm gate length, a unit gain frequency of 565 GHz is observed. NST with 24 nm exhibits Gain Frequency Product value of 5.3 THz. The gain-to-power efficiency improvement from 0.048 µA−1 to 2.16 µA−1 is observed. A reversal of relationships of transconductance and other performance parameters with gate length is observed at 24 nm gate length. [ABSTRACT FROM AUTHOR]

Conventional spin transfer torque (STT) magneto-resistive random access memory (MRAM) generally includes a bulk n-channel MOS (NMOS) transistor as an access device that provides equal drive current in standalone conditions in both the directions. However, the switching current requirement of magnetic tunnel junctions (MTJs) in STT MRAM is highly asymmetric (2 to 3:1). With conventional access devices, the excess write current in one direction maps to unnecessarily higher power dissipation. Hence, in this paper, a novel STT MRAM cell with an asymmetric-dielectric (asymmetric- $k$ ) sidewall-spacer NMOS (ASNMOS) is presented. ASNMOS has different- $k$ sidewall spacers, i.e., one side high- $k$ and other side low- $k$ spacer. As desired, this novel ASNMOS provides asymmetric drive current and reduces the overall power dissipation. The proposed STT MRAM cell is analyzed with HSPICE simulations using calibrated Verilog-A models for access device and perpendicular magnetic anisotropy MTJ. The STT MRAM cell with the proposed ASNMOS exhibits up to 25% reduction in the dynamic power dissipation over the STT MRAM cell with the conventional symmetric NMOS as an access device. Moreover, ASNMOS-based cells shows higher reliability wherein the worst case current density through MTJ is reduced by 25%. [ABSTRACT FROM PUBLISHER]

During recent years, high- \(k\) spacer materials have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance that restricts researchers using these devices in high-performance circuits. For the first time, this paper demonstrates the usage of high-k spacer material with an optimized length for effective reduction of circuit delay and an improvement in robustness. An improvised symmetric dual- \(k\) spacer (SymD-k) underlap trigate FinFET architecture termed as SymD-k is employed for this purpose. From extensive 3-D simulations, this paper demonstrates that SymD-k device significantly improves overall circuit delay and robustness (noise-margins) with fully capturing the fringe capacitance effects. A CMOS inverter and a three-stage ring-oscillator (RO3) are adopted to carefully investigate the performances. In comparison with the conventional device, the SymD-k device speeds up the RO3 circuit by 27% and 33% using high-k spacer dielectric HfO2 and TiO2, respectively. However, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effect of underlap length and supply voltage on SymD-k-based RO3 delay over the conventional ones are also dealt in. [ABSTRACT FROM AUTHOR]

Underlap FinFET devices, or trigate transistors, are considered to be the most favorable substitute to the conventional bulk device below 22-nm technology node. However, their application in circuit design requires specific attention because of the fin width quantization and increased parasitic. This paper proposes a double dielectric or dual-k spacers technology to enhance the electrostatic integrity of underlap FinFETs. For the first time, we investigate the circuit performance such as that of static RAMs (SRAMs), based on the proposed dual-k spacer FinFETs. The proposed structure enhances SRAMs performance in terms of robustness, access times, and the leakage power during all possible modes of operation. The hold, read, and write-margin increases by 8.7%, 9.4%, and 10.4%, respectively, as compared with conventional FinFET SRAM. Furthermore, the read and write access times reduces by 56% and 17.1%, respectively. Moreover, the standby leakage power is also reduced by \sim73\% compared with the conventional FinFET-based SRAM while occupying same bit-cell area. [ABSTRACT FROM PUBLISHER]