76 results on '"Pal, Pankaj Kumar"'
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2. Nanosheet Transistor with Inter-bridge Channels for Superior Delay Performance: A Comparative Study
3. Effect of Process-Induced Variations on Analog Performance of Silicon based Nanosheet Transistor
4. Attention based hybrid deep learning model for wearable based stress recognition
5. Effect of Temperature on Performance of 5-nm Node Silicon Nanosheet Transistors for Analog Applications
6. Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor
7. Design of an area and energy-efficient last-level cache memory using STT-MRAM
8. FuSeR: Fusion of wearables data for StrEss Recognition using explainable artificial intelligence models
9. Multi-band Rectenna Integrated with Solar Cells for Microwave Energy Harvesting System
10. Power Supply Variations and Analog Performance of 5-nm Node Silicon Nanosheet Transistor
11. Tri-Gate FinFET Technology and Its Advancement
12. Dual-k Spacer Device Architecture and Its Electrostatics
13. Capacitive Analysis and Dual-k FinFET-Based Digital Circuit Design
14. Introduction to Nanoelectronics
15. Statistical Variability and Sensitivity Analysis
16. Design Metric Improvement of a Dual-k–Based SRAM Cell
17. Air-spacers as analog-performance booster for 5 nm-node N-channel nanosheet transistor
18. A Report About the National Seminar on “Contemporary Progress in Plant Sciences” (March 20–21, 2015); Organized by UGC Centre of Advanced Study-Department of Botany, The University of Burdwan
19. Effect of gate length on performance of 5nm node N-channel nano-sheet transistors for analog circuits
20. Impact of Size, Latency of Cache-L1 and Workload Over System Performance
21. Mixed-mode circuit simulations with 5 nm Node Nanosheet Transistors using TCAD
22. Classification of human heart signals by novel feature extraction techniques for rescue application
23. Analysis of Nanosheet Field Effect Transistor (NSFET) for device and circuit perspective
24. A Narrow Band Cascode Source Degeneration Low Noise Amplifier with π-Input Matching at 5 GHz Frequency
25. Novel Feature Extraction Algorithm using DWT and Temporal Statistical Techniques for Word Dependent Speaker’s Recognition
26. Effect of gate length on performance of 5nm node N-channel nano-sheet transistors for analog circuits.
27. An Advance Architecture of Magnetic Random Access Memory
28. SET Detection and Radiation Hardened Pipelined 8-Bit ADC Using 180 Nm Technology
29. Spacer Engineered FinFET Architectures
30. A Report About the National Seminar on “Contemporary Progress in Plant Sciences” (March 20–21, 2015); Organized by UGC Centre of Advanced Study-Department of Botany, The University of Burdwan
31. Performance Enhancement of STT MRAM Using Asymmetric- Sidewall-Spacer NMOS
32. A detailed capacitive analysis of symmetric and asymmetric dual-k FinFETs for improved circuit delay metrics
33. A STUDY OF EFFECT OF PERINATAL ASPHYXIA ON THYROID HORMONE IN NEONATES
34. Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design
35. Highly reliable STT MRAM using fully depleted body and buried 4H-SiC NMOS
36. Enhanced device performance using lightly doped channel junctionless accumulation-mode FinFET
37. Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis
38. A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives
39. Investigation of Symmetric Dual- \(k\)Spacer Trigate FinFETs From Delay Perspective
40. High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications
41. Low-power and robust 6T SRAM cell using symmetric dual-k spacer FinFETs
42. Design Metrics Improvement for SRAMs Using Symmetric Dual-$k$ Spacer (SymD-$k$) FinFETs
43. Optimization by Vacuum Metallization for Reflector Antenna: A Multiple Beamformer
44. High-Performance and Robust SRAM Cell Based on Asymmetric Dual-$k$ Spacer FinFETs
45. Highly reliable STT MRAM using fully depleted body and buried 4H-SiC NMOS.
46. Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design.
47. Performance Enhancement of STT MRAM Using Asymmetric- $k$ Sidewall-Spacer NMOS.
48. Performance analysis of dual-k spacer at source side for underlap FinFETs
49. Investigation of Symmetric Dual- \(k\) Spacer Trigate FinFETs From Delay Perspective.
50. Design Metrics Improvement for SRAMs Using Symmetric Dual-k Spacer (SymD-k) FinFETs.
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