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To preferably regulate the charging current and decrease circuit complexity for parallel charging, a battery charger with variable charging current (VCC) and automatic voltage compensation (AVC) controls is presented. Based on the battery voltages, the VCC control not only dynamically maximizes the charging currents in both the trickle current (TC) and constant current (CC) stages but also prevents from damaging multiple batteries. Thus, the VCC control realizes safe charging and reduces charging time for parallel battery packs in the TC and CC stages. Owing to the battery’s parasitic resistance, a conventional charger changes from CC to constant voltage (CV) stage without approaching the rated voltage of the battery packs. The AVC control estimates the parasitic resistance and determines the proper transition timing from the CC to CV stage. Therefore, the duration of CC stage is prolonged and the CV charging time is reduced. Thanks to the VCC and AVC controls, the proposed battery charger can achieve charging time reduction and charging safety simultaneously. The experimental results verify that the periods of CC and CV stages are extended and shortened, respectively, and charging currents are maximized to the predefined values in the TC and CC stages. The maximum efficiencies in the CC and CV stages are up to 96.4%. Furthermore, compared to charging dual battery packs with conventional control, the proposed controls can save about half of total charging time.

This article presents a single-stage ac–dc light-emitting diode (LED) driver to achieve current regulation of red, green, and blue (RGB)-LED strings and ac–dc rectification with high power factor. The advantages of single-stage topology include single inductor, lower component counts, and smaller form factor. To adaptively and accurately regulate RGB-LED strings a switching capacitor control scheme is adopted with the properties of dynamic voltage difference detection and fast bus voltage hopping. The dynamic voltage difference detection precisely detects the voltage difference between the R- and GB-LED strings while the fast bus voltage hopping can immediately adjust the bus voltage level. The experimental results are shown to verify the theoretical analysis of the proposed LED driver, and the transient response time is less than 0.3 μ s, which is at least three orders faster than the previous work. The peak efficiency of the proposed LED driver is up to 88.6%.

This paper presents an active ripple cancelation (ARC) technique for reducing the switching harmonics of the output voltage of a dc–dc converter. An ARC module injects an ac current to accurately cancel the inductor current ripple while the switching converter provides the dc output current. As a result, the output spur of the switching converter can be reduced effectively. However, due to the ARC module, the proposed power converter includes two complex poles. To ensure the system stability and achieve accurate ripple cancelation, a proposed control method and an adaptive phase-lock circuit are utilized. Furthermore, the ripple cancelation capability is independent of duty cycle, load current, and other converter parameters. The measurement results demonstrate that the switching spur reduction with ARC technique can achieve 28 dB while the noise floor is kept the same.

A high-efficiency multimode battery charger with an adaptive supply voltage (ASV) control scheme is presented in this paper. The proposed battery charger includes a charging circuit and a dc–dc buck converter. The charging circuit automatically switches among trickle current (TC), constant-current (CC), and constant-voltage (CV) modes corresponding to the battery voltage while the buck converter with ASV control generates an ASV to closely track the battery voltage, leading to significant reduction in the power loss of the charging circuit. To further enhance the efficiency of the battery charger, zero-current detection and nonswitching control schemes are employed to decrease the power consumption of the buck converter in TC and CV modes. The battery charger was implemented with a 0.35- μ m CMOS 2P4M process. The experimental results are shown to verify the theoretical analysis of the proposed charger. The maximum efficiency of the overall system is 88.3%, and the maximum efficiency improvement between the proposed charger and the conventional linear charger with fixed supply voltage is up to 11.6%.

An LED driver consisting of dimmable current balancing circuits (CBCs) and a boost converter with drain voltage balance (DVB) and phase-shifted pulsewidth modulation (PSPWM) control schemes is presented. To reduce the power loss on conventional linear current regulators, CBCs are employed. The DVB control scheme is proposed to maintain a desired constant voltage across the CBCs, so as to increase current balance and achieve high efficiency of the CBCs. Thus, the bus voltage of the boost converter is adaptively regulated based on the DVB control. The PSPWM control scheme can alleviate the variation of the bus current provided by the boost converter. As a result, the transient ripple of the bus voltage can be reduced when the light-emitting diode (LED) strings are turned on and off. Furthermore, the utilization of DVB control is increased when the PWM dimming duty cycle becomes lower. The experimental results demonstrate that the minimum voltage among the CBCs is always kept at the lowest constant level while maintaining the required current passing through the LED strings. The efficiency of the CBCs is kept almost the same for different LED currents and is over 95%. Thus, a high-efficient parallel-string dimmable LED driver with simple circuitry can be achieved.

In this paper, a feed-forward control (FFC) scheme is presented for line transient improvement in a boost converter. Since the FFC scheme adopts two auxiliary lines and the modulation signal with adjustable slope, an accurate duty cycle cab be determined immediately and the compensator output can be maintained constant when the input voltage varies. Hence, the transient ripple of output voltage of the boost converter with FFC scheme can be minimized effectively. The measured results verify that the FFC scheme significantly decreases output transient ripple under input voltage variations and achieves high efficiency concurrently.

A two-input floating buck (TIFB) converter is proposed to decrease voltage stress dramatically, while achieving high power efficiency for LED lighting systems. Its power transistors can also be low voltage and on chip to reduce cost with small chip area. A proposed variable off-time (VOT) control with an on-chip current sensor would detect the peak inductor current and adjust the off-time period dynamically depending on the number of series lighting-emitting diodes (LEDs) and its input voltage. High-accuracy LED current can thus be realized with little additional power. The TIFB converter’s operating principle and the VOT control scheme are described in detail. Experimental results of a prototype in 0.25- $\mu \text{m}$ 5-V CMOS process are shown to verify the theoretical analysis of a proposed LED driver.

A continuous-conduction mode (CCM) noninverting buck–boost (NBB) converter with a fast duty-cycle calculation (FDCC) control and duty-cycle locking strategy is proposed in this paper. Utilizing auxiliary and adjustable slopes of the modulation signal, the FDCC control not only rapidly determines an accurate duty cycle but also keeps the compensator output constant when the input voltage changes. The theoretical dc value of the numerator of the closed-loop line-to-output voltage transfer function is equal to zero whether the CCM NBB converter operates in boost or buck mode. It indicates that adopting the FDCC control can achieve ideal feedforward compensation for CCM buck and boost operations. Consequently, the output transient ripple of the CCM NBB converter with FDCC control can be eliminated significantly regardless of the unit-gain bandwidth of the NBB converter. To alleviate pulse skipping and to avoid changing buck and boost modes frequently, a duty-cycle locking method is adopted in the transition region of the buck and the boost. Hence, the duty-cycle locking method enhances power conversion and maintains the output voltage. The experimental results demonstrate that the proposed control schemes not only effectively reduce the line transient ripple but also obtain high efficiency in a wide range of input voltage.

To reduce circuit complexity and better control the charging current for parallel charging, a switching-based charger with an adaptive hybrid duty cycle control (AHDCC) for multiple batteries is presented. Depending on the voltage difference of the batteries, the AHDCC mechanism automatically delivers a different amount of energy to each battery to realize battery voltage balance and reduce power losses. Since an intermittent charging method is adopted in the constant current (CC) mode, the effect of voltage drop across the battery's parasitic resistor can be removed, and thus the charging time in CC mode is prolonged. AHDCC adjusts the charging current, prolongs the charging period in CC mode, and entirely turns on the auxiliary switches in the constant voltage mode. As a result, the functionalities of fast charging and battery voltage balance can be realized concurrently. The experimental results demonstrate that the peak efficiency of the charger is up to 89.4% and the total charging time of two batteries is slightly smaller than that of a single battery.

This study presents a hysteresis prediction voltage control (HPVC) technique based on a predictive control method with early actions to solve ringing circumstances and to alleviate transient ripples. A dc-dc converter switches from a voltage-controlled pulse width modulation mode to the proposed HPVC mode during transient. Hence, the dc-dc converter has a fast transient response when its load current varies. The converter also keeps constant switching frequency during the steady state. The ringing, recovery time and transient ripples can be effectively reduced without paying a price of increasing the output capacitor of the power converter. A prototype chip with the proposed HPVC technique was implemented in a 0.35-μm CMOS technology. The experimental results show that the recovery time is less than 10 μs for a 400-mA load current change.

This paper presents a dc-dc converter with self-regulated output voltage (SROV)and phase shift PWM (PSPWM)control methods for multiple LED strings. The LED driver is composed of a boost converter and dimmable current balancing regulators (CBRs). Compared with traditional linear current regulator, the CBR is adopted to reduce power consumption. To keep a designed constant voltage on the CBRs, the output voltage of the boost converter is dynamically adjusted with the SROV control method. It results in high efficiency and current balance of the CBRs and prevents output voltage oscillation. The PSPWM control is employed to mitigate the output current variation supplied by the boot converter, leading to smaller output transient ripple when the PWM dimming signals are changed. The CBRs and control circuits were fabricated with a 0.35-μm standard CMOS technology. The experimental results demonstrate the theoretical analysis of the proposed LED driver.

The current boosting module (CBM) is proposed to be implemented in an error amplifier (EA) for improving the load transient of a dc–dc converter. To enhance the slew rate of the EA during transient, the CBM is adopted to raise/reduce the gate voltages of the output-stage transistors of the EA for enhancing its current driving capability with simple circuitry. Moreover, to save power consumption in steady state, the accelerative mechanism of the EA is turned off. A buck converter with CBM is implemented with 0.35 μm 2P4M complementary metal–oxide–semiconductor process. The experimental results demonstrate that the recovery time and transient ripple of the buck converter are improved by over ten times and two times, respectively, compared with those of the buck converter without CBM, for a 450 mA load current change. The maximum power conversion efficiency is 92.8% when the input and output voltages are 4 and 2.5 V, respectively. Hence, the buck converter with CBM can concurrently fulfil the functionalities of fixed switching frequency and fast load transient.

This paper proposes a dual-transformer active-clamp forward converter (DT-ACFC) with nonlinear conversion ratio (NCR), which combines two forward converter units. Since only two active switches are needed, the cost and the circuit complexity can be lowered. To reduce switching loss, the proposed converter fulfills zero-voltage switching by employing the leakage inductance of the transformer and additional resonant inductance. By paralleling the transformer secondaries and changing the circuit architecture of each secondary side, we can make the output load current evenly shared among four output inductors such that the current stress and conduction losses of the output rectifiers can be decreased significantly. Moreover, the nonlinear step-down conversion ratio leads to a high duty utilization ratio for the proposed converter. Therefore, the DT-ACFC with NCR is suitable for applications of high output current and a wide input voltage range. Experimental results are shown to verify the theoretical analysis of the proposed forward converter.

This paper presents a multimode battery that is composed of a dc-dc buck converter and a charging circuit. The charging circuit can provide a ripple-free charging current and automatically switches among trickle current (TC), constant-current (CC), and constant-voltage (CV) stages depended on the battery voltage. The buck converter with a dynamic voltage tracking (DVT) control produces a dynamic supply voltage to closely follow the battery voltage, resulting in considerable efficiency improvement of the charging circuit. To reduce power loss of the buck converter, non-switching control and zero current detection are utilized to increase the efficiency of the battery charger at CV and TC stages. The battery charger was designed with a 0.35-μm CMOS technology. The simulation results are shown to verify the theoretical analysis of the proposed charger.

This paper presents a switching-based charger with a time division fast charging (TDFC) control to decrease circuit complexity and charging time for multiple batteries. Time division scheme can deliver a different energy amount to each battery to achieve battery voltage balance and remove the effect of the battery's parasitic resistor to prolong the charging time in constant current (CC) stage. To reduce charging time, the charging current in CC stage is regulated and the auxiliary switches are wholly turned on in constant voltage stage. Hence, the functionalities of battery voltage balance and fast charging can be achieved simultaneously. Experimental results are shown to verify the theoretical analysis of the proposed charger.

Techniques of a dual-path error amplifier and two capacitor multipliers for providing on-chip frequency compensation and soft-start function are proposed in this paper. The concept of the dual-path error amplifier is to use two currents to charge and discharge a compensation capacitor simultaneously. As a result, the equivalent capacitance is enlarged significantly with little additional power and silicon area. The dc-dc converter with the dual-path architecture also has great performance in transient response because the compensation capacitor is reduced significantly. For the soft-start function, the subtractive-type and time-average capacitor multipliers are used to relax the restriction of the capacitance and the charging current. Consequently, it is easy to integrate the soft-start capacitance into a chip and the output overshoot voltage can be suppressed. A prototype converter fabricated with TSMC 0.35-μm 2P4M CMOS process verifies the effectiveness of the techniques of a dual-path error amplifier and two capacitor multipliers. Experimental results demonstrate the converter stability, transient response, and soft-start function. The transient recovery time and transient ripple are less than 20 μs and 25 mV, respectively, for the load current swing from 50 to 500 mA. Moreover, the soft-start time is up to 8 ms. With the proposed techniques, the external pins of the dc-dc converters are minimized and their performance is improved significantly.

This study proposes a forward converter with non-linear step-down conversion ratio. In comparison with traditional forward converters, it has a higher duty utilisation ratio. Furthermore, the two output inductors can equally divide the load current, and therefore the current stress of inductors and output diodes can be reduced. Thus, the proposed converter is suitable for high step-down applications. On the primary side, active-clamp control can nullify the voltage spike of main switch while also achieving zero voltage switching operation of the main switch and auxiliary switch, hence the switching loss can be reduced. Detailed analysis and design of the proposed converter are described. Experimental results are recorded for a prototype converter with an AC input voltage ranging from 90 to 264 V, an output voltage of 12 V, and an output power of 240 W.

The voltage boosting control (VBC) is presented to achieve low-power and high slew-rate error amplifier for enhancing the load transient response of dc-dc converters. The VBC is employed to increase/decrease the gate voltages of the output-stage transistors of the error amplifier, leading to large current driving capability with simple circuitry during transient. In addition, the accelerative scheme of the error amplifier is switched off in steady state for power saving. A buck converter with the VBC method is designed with 0.35-µm 2P4M CMOS technology. Compared without the VBC, the experimental results show that the output voltage variation and recovery time of the buck converter with the VBC are enhanced by over two times and ten times, respectively, for load current change between 50 mA to 500 mA.

A pair of complementary class-A buffers with voltage boosting method and improved frequency compensation is proposed. The buffer driving capabilities are enhanced by adding small auxiliary transistors to pull-up/pull-down the gate voltages of the buffer output transistors to improve the transient response. The auxiliary transistors are turned off for power saving in the steady-state operation. The proposed frequency compensation is more area-efficient than the Miller compensation method and hence maintains the high output voltage slew rate of the buffer. The measured static current of each buffer with the proposed circuits consumes 3 μA under a supply voltage of 5 V. The buffer settling times of the rising and the falling edges with a capacitance of 600 pF for an input swing of 5 V are 3.3 and 1.7 μs, respectively. The core size of the buffers including the compensation capacitance is 82 × 101 µm2 and the buffer can be stable when a load capacitance changes from 5 to 600 PF. Hence, the proposed output buffers concurrently achieve a fast response and are suitable for a wide range of load capacitances.

This paper presents an inductor current average control (ICAC) method that minimizes the undesirable transient glitches in dc-dc converters using a frequency-hopping pulsewidth modulation control. The analysis in this paper shows that without careful control of the frequency-hopping instant for the dc-dc converters, the transient glitches can be rather large in magnitude and may interfere with the modulated signal to be transmitted from a mobile communication device. The ICAC technique selects the frequency-hopping instant such that the average inductor current is undisturbed when the switching frequency hops. The measurement result shows that the ICAC technique can suppress the transient spurs by 14.1 dB and the voltage of the transient glitches by 65.3%.

This paper presents a compact 10-bit digital-to-analog converter (DAC) for LCD source drivers. The cyclic DAC architecture is used to reduce the area of LCD column drivers when compared to the use of conventional resistor-string DACs. The current interpolation technique is proposed to perform gamma correction after D/A conversion. The gamma correction circuit is shared by four DAC channels using the interleave technique. A prototype 10-bit DAC with gamma correction function is implemented in 0.35 μm CMOS technology and its average die size per channel is 0.053 mm2, which is smaller than those of the R-DACs with gamma correction function. The settling time of the 10-bit DAC is 1 μs, and the maximum INL and DNL are 2.13 least significant bit (LSB) and 1.30 LSB, respectively.

This paper presents an efficient CMOS dc-dc converter with fast transient recovery. A fast-transient control operating in conjunction with a linearly scaled gate-driving technique is used to concurrently improve the transient response and light-load efficiency of a dc-dc converter. The controller operates under a pulse-width modulation mode during steady state and enables a saturation mode during transient to attain fast transient response. The linearly scaled gate-driving technique optimizes the gate-driving voltage with respect to the changing load leading to lower gate-driving loss and better light-load efficiency. A prototype chip was implemented using a commercial 0.35-μm CMOS process to validate the proposed techniques. The measurement result shows a 5% increase in light-load efficiency and achieves an overall maximum efficiency of 90%. Moreover, the transient recovery time of a 450 mA step load change is less than 9 μs.

An LED driver composed of a boost converter and dimmable current regulators with adaptive voltage feedback control (AVFC) is proposed. The AVFC is fulfilled with two diodes, one integrator, and one subtractor to sense the voltage variation among the current regulators and then to generate an adaptive reference voltage. According to the reference voltage, the output voltage of the boost converter is automatically regulated, so as to keep a minimum voltage on the current regulator and maintain the required LED-string current. A prototype driver implemented with 0.35-µm 2P4M CMOS process validates the proposed technique. The simulation result shows that the output voltage of the boost converter is dynamically adjusted to compensate for the voltage alteration on the current regulators.

This paper presents a random frequency hopping with triangular ramp control for harmonic reductions in a dc-dc converter. The relationship between “the sawtooth and triangular ramp signals” and the inductor current is analyzed, and the two ramp signals are implemented into the converter to compare the variation of output voltage. When the switching frequency hops, using triangular ramp keeps the small variation of the average inductor current. A prototype buck converter implemented 0.35μm 2P4M CMOS process verifies the effectiveness of the proposed method. Compared with eight and single switching frequencies, the proposed frequency hopping circuit can suppress the output harmonics by 21.9 dB from simulation results. Without increasing the output inductance or capacitance, the harmonics can be decreased dramatically.

This paper presents a power-level tracking power amplifier with reduced spurious emission by utilizing a dc-dc converter with frequency-hopping capability. Measurements were performed for a wideband code-division multiple access (W-CDMA) signal and an EDGE signal at 836.5 MHz. The results show a two times improvement in average efficiency while showing negligible spectral degradation for the W-CDMA standard. For the EDGE standard, the efficiency was also improved by a factor of 2 for medium power levels compared to not using a dc-dc converter. Moreover, the spurious emissions were improved by up to 4.5 dB using the proposed technique.

This paper presents a novel fast transient recovery module to improve the transient response of DC-DC converters to meet the challenging power supply requirement of fast dynamic load changes. The current-pump module operates only at transient state to provide additional current injection and current drain for step-up and step-down loads, respectively. The dual-mode control is proposed to switch the voltage control mode of DC-DC converters to hysteretic control mode during transient. The measurement results show that the fast transient recovery module and dual-mode control can improve the recovery time of DC-DC converters by more than an order.

This paper presents a novel dual-current pump module (DCPM) to improve the transient response of dc-dc converters. The DCPM operates only during transient to provide two additional current injections for step-up load and current drains for step-down load. Due to the two current pump paths, the current stress on the switches of the DCPM is also reduced. The measurement results show that the DCPM can enhance the dynamic recovery time of the buck dc-dc converter by more than an order.

This paper proposes a dual-path frequency compensation (DPFC) for implementing on-chip error amplifier (EA). The DPFC uses two operation amplifiers to simultaneously charge and discharge a compensation capacitor. As a result, the equivalent capacitance is significantly multiplied with small additional power and silicon area. Since the slew rate of the EA is increased owing to the small compensation capacitance, the transient response of the buck converter is also enhanced dramatically. A laboratory converter with the DPFC is implemented with 0.35-μm CMOS process. Simulation results demonstrate the converter stability and transient response. The transient recovery time is less than 4 μs for load current changing from 500 mA to 50 mA. With the DPFC, the compensation capacitor is shrunk significantly and no compensation resistor is needed.

A Simple signal compensating strategy for digital inverter is proposed. Because of the non-ideal characteristics from the transformer and MOSFET modules, the output waveforms in positive and negative cycles are non-equaled. This phenomenon will cause the inductive load saturated, and the switches get damaged easily. Thus, the proposed strategy is to combine pulse signal and the reference signal of inverter for adjusting the width and amplitude of pulse signal. The average voltage of the combined signal helps to compensate the DC offset. The strategy is implemented by using built-in low resolution PWM digital controller which has auto adjustment function for the non-equaled output waveforms.

A pair of complementary class-A buffers with voltage boosting technique is presented. The driving capabilities of the buffers are improved by adding auxiliary transistors to pull-down/pull-up the gate voltages of the buffer output transistors to induce large current for discharging/charging, respectively. To save power, the auxiliary transistors are turned off in steady state operation. Compared to the previous works, the size of these auxiliary transistors can be significantly reduced when the gate-source voltage boosting is adopted. The measurement results showed that each buffer consumes 3 μA static current under supply voltage of 5V, and its settling times of the rising and falling edges with a capacitance of 600 pF for an input swing of 5 V are 3.5 μs and 1.8 μs. The settling time of the buffer with the proposed technique is faster than that of the buffer without it by about 2 times. Hence, the proposed output buffers realize fast response and maintain low power consumption.

This paper presents a soft-start circuit that adopts a pulse-skipping control to prevent inrush current and output voltage overshoot during the start-up period of dc-dc converters. The purpose of the pulse-skipping control is to significantly restrain the increasing rate of the reference voltage of the error amplifier. Thanks to the pulse-skipping mechanism and the duty cycle minimization, the soft-start-up time can be extended and the restriction of the charging current and the capacitance can be relaxed. The proposed soft-start circuit is fully integrated on chip without external components, leading to a reduction in PCB area and cost. A current-mode buck converter is implemented with TSMC 0.35-μm 2P4M CMOS process. Simulation results show the output voltage of the buck converter increases smoothly and inrush current is less than 300 mA.

This paper shows that the optimal driving voltages of power MOSFETs can be well modeled by a linear function of the load current. Thanks to the linear model, the self-scaling gate drive technique is proposed to improve the light-load efficiency of DC-DC converters by reducing gate driving loss. The gate drive voltage is scaled dynamically with respect to load current change. The proposed self-scaling gate drive technique can attain about 5.8% incremental enhancement on light-load efficiency.

This paper presents a spurious emission suppression technique for RF power amplifiers using frequency-hopping DC-DC converters. The frequency-hopping technique changes the switching frequency of the DC-DC converter dynamically and reduces the peak spur created by using a DC-DC converter with a radio frequency power amplifier. The use of this technique can also reduce the size of the external passive components used for reducing the ripple voltage of the DC-DC converter, which creates the radio frequency spurs. A prototype system using a cellular band power amplifier operating at 836.5 MHz and a commercial DC-DC converter was built to verify this technique. Measurement results show by frequency-hopping between eight frequencies, the maximum radio frequency spur can be reduced by more than 11 dB.