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This paper deals with the design and experimental results of the Engineering Model of a Solid State Power Amplifier (SSPA) based on 100 nm gate length Gallium Nitride on Silicon technology and spatial power combining techniques, targeting Ka-band downlink SatCom applications. In the overall bandwidth (17.3-20.2 GHz), the SSPA delivers up to 125 W of output power with a minimum efficiency and gain of 24% and 70 dB, respectively.&nbsp

This paper presents the design, electromagnetic simulation strategies and experimental characterisation of a two‐stage stacked‐FET cell in a 100 nm GaN on Si technology around 18.8 GHz, suited for Ka band satellite downlink applications. A good agreement is found between the electromagnetic simulations and the measured performance on the manufactured prototype, thus demonstrating that a successful voltage combining architecture can be obtained in the frequency range of interest with the selected topology, based on a symmetric fork‐like connection between the transistors. This proves the effectiveness of an appropriate electromagnetic simulation set‐up in correctly predicting the crosstalk, which typically affects this structure, leading to a correct stacking operation.

In this paper, the design, fabrication, and measurements of an S band multi harmonic tuned power amplifier in GaN technology is described. The amplifier has been designed by exploiting second and third harmonic tuning conditions at both input and output ports of the active device. The amplifier has been realized in a hybrid form, and characterized in terms of small and large signal performance. An operating bandwidth of 300 MHz around 3.55 GHz, with 42.3 dBm output power, 9.3 dB power gain and 53.5% power added efficiency PAE (60% drain efficiency) at 3.7 GHz are measured.

The 9th Microwave and Radar Week (MRW 2020) was held in Warsaw the capital of Poland, on 5–7 October 2020 [...]

This letter presents an innovative stacked cell, where the common source device is split in to two smaller devices leading to a more compact and symmetric structure, with almost negligible parasitics associated with the transistor connection. This novel configuration is rigorously compared, for the first time, with the two classical approaches commonly adopted to physically connect the two devices. The three different layouts are fabricated in gallium nitride technology for high-frequency power applications and experimentally compared by means of an extensive measurement campaign performed on several loads and in different bias conditions, ranging from class AB to C. The proposed novel configuration outperforms the other two in all conditions, thanks to the advantages of adopting two smaller devices with reduced parasitics, higher gain, and higher power density. These features are common to different technologies, thus making the novel topology widely applicable for the design of high-frequency stacked cells.

This paper discusses the design steps and experimental characterization of a monolithic microwave integrated circuit (MMIC) power amplifier developed for the next generation of K-band 17.3–20.2 GHz very high throughput satellites. The technology used is a commercially available 100-nm gate length gallium nitride on silicon process. The chip was developed taking into account the demanding constraints of the spacecraft and, in particular, carefully considering the thermal constraints of such technology, in order to keep the junction temperature in all devices below 160°C in the worst-case condition (i.e., maximum environmental temperature of 85°C). The realized MMIC, based on a three-stage architecture, was first characterized on-wafer in pulsed regime and, subsequently, mounted in a test-jig and characterized under continuous wave operating conditions. In 17.3–20.2 GHz operating bandwidth, the built amplifier provides an output power >40 dBm with a power added efficiency close to 30% (peak >40%) and 22 dB of power gain.

The stacked power amplifier is a widely adopted solution in CMOS technology to overcome breakdown limits. Its application to compound semiconductor technology is instead rather limited especially at very high frequency, where device parasitic reactances make the design extremely challenging, and in gallium nitride technology, which already offers high breakdown voltages. Indeed, the stacked topology can also be advantageous in such scenarios as it can enhance gain and chip compactness. Moreover, the higher supply voltages and lower supply currents beneficially impact on reliability, thus making the stacked configuration an attractive solution for space applications. This paper details the design of two stacked cells, differing in their inter-stage matching strategy, conceived for space applications at Ka-band in 100 nm GaN-on-Si technology. In particular, the design challenges related to the thermal constraints posed by space reliability and to the electro-magnetic cross-talk issues that may arise at millimeter-wave frequencies are discussed. The best cell achieves at saturation, in simulation, 3 W of output power at 36 GHz with associated gain and efficiency in excess of 7 dB and 35%, respectively.

A wideband 4-way combined power amplifier (PA) in a $0.13-\mu \mathrm{m}$ BiCMOS process is presented. The overall PA is based on four unit cells of 3-stage cascode PA, which is adopted for larger output power and higher gain. Load pull simulations are done to optimize the unit cells together with the 4-way combiner for wideband characteristics. With the assistance of hicum and vbic models, the overall PA shows a peak gain of 30dB at 126GHz with the 3-dB bandwidth higher than 80GHz. Under large-signal excitation, the PA delivers a maximum output power greater than 17.5dBm at 120-180 GHz with peak PAE higher than 5%. The PA can be used for various future D-band applications. Measurements are on the way and will be presented into the final contribution.

This work presents a self-biased 2-stacked power amplifier cell that shows, in simulations, an output power in excess of 33 dBm and gain and power added efficiency (PAE) above 6 dB and 27 %, respectively, over a 33.5 GHz to 39.5 GHz bandwidth. The cell has been developed on a commercial 100 nm GaN-on-Si process, applying space derating rules at center frequency, where the output power is almost 33.8 dBm, the associated gain is higher than 7 dB and PAE is above 35 %.

This paper reports the design, manufacturing and test of a power amplifier, based on a newly power bar device developed on GaN technology, conceived for L-Band applications. The realized active device is a single 10mm active periphery GaN HEMT, realized by paralleling eight 1.25 mm-gate periphery devices (10x125 μm), fabricated on a 0.5 μm GaN-on-SiC technology by Leonardo company. The power amplifier realized with this device is tested in pulsed condition, demonstrating an output power higher than 40 W at 30 V of drain voltage supply, with an associated efficiency of 50 % at 3 dB of gain compression.

This article presents two broadband frequency multiplier chains (FMCs) fabricated with a standard 130-nm SiGe BiCMOS process. In both solutions, a broadband push-push frequency doubler (x2) operating at 220–360 GHz was employed. In order to properly drive such a doubler, with sufficient input power and bandwidth, two different power amplifiers (PAs) have been adopted: the former is based on a cascode configuration and the latter is based on a stacked topology. In addition, a D-band frequency quadrupler (x4) has been integrated before the PAs and doubler, to complete the design of frequency eighth tupler (x8) chains. The first FMC with the cascode PA achieves peak output power of 2.3 dBm, with maximum conversion gain (GC) and bandwidth of 15 dB and 127 GHz, respectively. The second FMC with the stacked PA delivers a saturated output power of 2.5 dBm, with a maximum GC and a bandwidth of 12 dB and 72 GHz, respectively. The two FMCs consume maximum dc power of 0.537 and 0.542 W. The complete design procedure of the FMCs is presented in this article. To the best of our knowledge, the reported bandwidth is state-of-the-art and widest among SiGe based FMCs.

In this paper we investigate the complexity of the characterization of electron devices with microwave load-pull systems when harmonically-tuned classes of amplification are adopted. In particular, we highlight the effects of the transistor dynamic nonlinearities on the load impedances at the transistor current-generator plane.

This paper presents the design of a balanced power amplifier (PA) using a 130-nm SiGe BiCMOS process. The PA consists of three stages, each based on cascode topology. The design of the PA was optimized using low-Q matching networks for the D-band applications. The results based on EM-simulation of the PA, with assistance of vbic and hicum models for the transistor, demonstrate an average peak gain of 26.5 dB with the 3-dB bandwidth higher than 80 GHz. In terms of large-signal, the PA provides an output power and PAE larger than 14 dBm, and 4 percent, respectively, in the D-band. Moreover, it provides an output power greater than 13 dBm at 110–190 GHz. The PA is highly suitable to drive frequency multipliers for the development of broadband sub-THz signal sources. The future work includes measurement of the PA.

Highly resistive (HR) silicon (Si) can behave as a switch when illuminated by optical source of suitable wavelength. Different reconfigurable passive structures, such as filters, waveguides, and antennas, can be constructed using such silicon switches. This letter presents experimental characterization of high and low resistive (HR & LR) silicon for switching application. In the experiment, HR Si is modeled on a switched transmission line by halogen lamp and a laser source. The experiment of utilizing halogen lamp for Si switch characterization is cost‐effective and can assist engineers in designing reconfigurable antennas. In future, this experiment could be utilized in designing novel reconfigurable antennas. H2020 ITN CELTA. Grant Number: 675683

This paper presents the design of a D-band frequency quadrupler (FQ) based on two cascaded frequency doublers. Each doubler relies on the bootstrapped Gilbert cell (GC) mixers. The FQ is developed with a standard 130-nm SiGe BiCMOS process. It consists of fully integrated input and output baluns, frequency doublers, and matching networks. The design of the FQ was optimized via single-ended matching networks to reduce the chip area and increase bandwidth. The results based on the EM-simulation of FQ with the assistance of the hicum model for the transistor, demonstrate a peak conversion gain and output power of 25 dB and 5 dBm, respectively at 130 GHz. The FQ shows a 3-dB bandwidth higher than 84 GHz with an nth harmonic rejection of at least 16 dBc. The FQ can be exploited in various systems design for different D-band applications. The future work includes measurement of the FQ.

This work presents an experimental investigation of class E power amplifier with parallel shunt network along with two similar amplifier obtained by adding series-connected parallel resonant tanks tuned for the second (class E/F3) and the third harmonics with duty ratio of D=0.33. The aim was obtaining of decreasing of maximum drain-source voltage together with high efficiency remaining. The experimental results shown about 0.6 W output power with 80% efficiency and reducing of drain-source voltage up to 2.5 times of voltage supply.

Highly Efficient power combining techniques are mandatory for developing solid state power amplifiers (SSPAs) for high frequency space applications. Indeed, SSPAs are designed starting from medium power components, in the range of few watts, that are combined in such a way that the equipment efficiency is kept as maximum as possible. Planar structures such as branchlines or Wilkinson provide good isolation between ports but their losses become prohibitive when both peak power and frequency are in the range of hundreds of watt and tens of GHz, respectively. In these cases, waveguide structures result to be the most appropriate. On this way, the paper presents the design and experimental characterization of two distinctive structures conceived for spatially combine sixteen 10W Gallium nitride monolithic microwave integrated circuit for realizing a Ka-band (17.3 GHz–20.2 GHz) SSPA with more than 125W of saturated output power.

This paper presents the design of a wideband on-chip dielectric resonator antenna (DRA) operating at sub-THz frequencies. The DRA consists of inverted E-shaped on-chip driver, a low-permittivity supporter, and a dielectric resonator (DR). Substrate integrated waveguide (SIW) cavity backed on-chip antenna with L-probe feeding mechanism is adopted for the driver at 350 GHz. A standard 130-nm SiGe BiCMOS back-end process is employed in its design. The input matching, gain, and radiation efficiency of the on-chip driver are enhanced by placing a supporter and a DR on top of it. From full-EM simulations, the DRA achieves the -10 dB impedance bandwidth of 65 GHz (18.5%) with peak gain of about 10 dBi and radiation efficiency of 75% at 350 GHz. The developed antenna is highly suitable for future broadband front-end systems operating above 300 GHz.

This paper presents a four-way combined G-band power amplifier (PA) using a 130-nm SiGe BiCMOS technology. A 185-GHz three-stage single-ended PA based on cascode topology with two driver stages and a power stage is designed. To combine output power of four single-ended PAs, a low-loss four-way reactive power combiner is designed. The developed PA shows a saturated output power of 18.1 dBm with peak gain of 25.9 dB and PAE of 3.5 % at 185 GHz. In addition, the PA provides a 3 dB and 6 dB bandwidth of 27 GHz and 42 GHz, respectively. To the best of our knowledge, the measured power reported in this paper is the highest for SiGe BiCMOS PAs in G-band.

In this paper, we reported the design of single-ended power amplifier (PA) delivering an output power greater than 12 dBm at 185 GHz. The PA is designed using 130-nm SiGe BiCMOS technology. It consists of a power stage and two driver stages. These stages are designed to have cascode topology under class A biasing. EM simulation of the designed PA has been performed with ADS momentum. With the HICUM model, the PA shows a saturated output power (P sat ), maximum gain, and power added efficiency (PAE) of 12.4 dBm, 27 dB, and 7% respectively at 185 GHz. The PA shows more than 10 dBm of $P_{sat}$ from 150–205 GHz with PAE more than 4%. The 3 dB small signal gain bandwidth is 28 GHz. Such performances are state of the art for single-ended PAs based on SiGe HBTs.

This contribution presents the design of a Monolithic Microwave Integrated Circuits (MMIC) power amplifier (PA) developed for radar applications in the upper Ka-band (35GHz - 40GHz). The MMIC is designed by using a $0.1 \mu \mathrm{m}$ Gallium Nitride on Silicon (GaN-on-Si) millimetre wave process and employs a single-ended, four-stage configuration for an enhanced gain. The designed power amplifier can provide 4W of output power with an associated gain of at least 19dB and minimum 25% of power added efficiency (PAE) in the targeted frequency range.

In this paper, we report the design of a D-band modified Marchand balun using IHP's 130-nm SiGe BiCMOS backend process. The design of the balun is based on three asymmetric coupled transmission lines, which reduce the amplitude and phase imbalance. The three asymmetric lines improve the odd mode capacitances, which increase the even/odd mode impedance ratio over wide bandwidth. Thus, wider bandwidth can be achieved with low phase and amplitude imbalance. The balun is EM simulated with ADS momentum and Sonnet. The −10 dB reflection coefficient $(S_{11})$ bandwidth of the balun is 136 GHz. It shows phase imbalance less than 7 degree and amplitude imbalance of ± 1dB from 94 to 177 GHz. Such performances of the balun make it an ideal candidate for various broadband differential circuits.

Very high-power and high-efficiency microwave applications require waveguide structures to combine/divide the power from/to a variable number of high-power solid-state devices. In the literature, among the different waveguide configurations, those capable of providing the maximum output power show a limited relative bandwidth. To overcome this limitation, in this paper a full-band (40%) waveguide power divider/combiner specifically designed for high-power applications (up to several kW) is presented. The proposed structure uses an evolved turnstile junction with a standard rectangular waveguide common port, rotated 45&deg, with respect to its central axis, to divide/combine the signal to/from the four output/input rectangular ports. The inclusion of an oversized central cavity together with circular and rectangular waveguide impedance transformers at the common port allows the achievement of a full-band operation with excellent electrical performance, while maintaining a very simple and compact configuration. Only two layers of metal are required for the physical implementation of this structure in platelet configuration. A prototype has been designed covering the full Ka-band (26.5&ndash, 40 GHz), showing an excellent measured performance with around 30 dB of return loss, 0.18 dB of insertion loss, and less than 1.5&deg, of phase imbalance.

This paper presents a single stage Class F-C power amplifier working at S-band. It achieves PAE higher than 60% and an output power of 37 dBm over frequency range 2.2 GHz to 2.47 GHz. The approach of gate harmonic control is adopted into the design. By manipulation of the 2nd harmonic at gate node, the proper phase relationship between 3rd harmonic and the fundamental one at the drain is obtained, in order to realize a Class F-C PA. The design procedure and the feasibility of harmonic manipulation at the input is also presented in this paper.