Search

Your search keyword '"Paraschiv, Vasile"' showing total 108 results

Search Constraints

Start Over You searched for: Author "Paraschiv, Vasile" Remove constraint Author: "Paraschiv, Vasile"
108 results on '"Paraschiv, Vasile"'

Search Results

4. A highly reliable 3-D integrated SBT ferroelectric capacitor enabling FeRAM ceiling

5. Fabrication challenges in integrating self-assembled block copolymer process in semiconductor devices

7. Sulfonic acid-functionalized gold nanoparticles: A colloid-bound catalyst for soft lithographic application on self-assembled monolayers

8. Kinetic stabilities of double, tetra-, and hexarosette hydrogen-bonded assemblies

9. Nanostructures via noncovalent synthesis: 144 hydrogen bonds bring together 27 components

16. (Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

17. (Invited) Vertical Nanowire FET Integration and Device Aspects

19. Thin-Silicon Injector (TSI): An All-Silicon Engineered Barrier, Highly Nonlinear Selector for High Density Resistive RAM Applications

22. Influence of crystallographic orientation on etch properties of TiN

23. Molecular 'chaperones' guide the spontaneous formation of a 15-component hydrogen-bonded assembly

24. Functionalized Hydrogen-Bonded Assemblies as Templates for Metal-Containing Arrays of Nanorods

27. Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

30. STT MRAM patterning challenges

32. (Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

35. Work-Function Engineering for 32-nm-Node pMOS Devices: High-Performance TaCNO-Gated Films

37. Metal/High-K Interface Interactions Upon High Temperature Annealing - Are They Cause of Workfunction Changes

39. Wet Etch Characteristics of Hafnium Silicate Layers

46. A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond.

49. Profile control of novel non-Si gates using BCl3/N2 plasma.

50. A Highly Reliable 3-D Integrated SBT Ferroelectric Capacitor Enabling FeRAM Scaling.

Catalog

Books, media, physical & digital resources