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123 results on '"Parihar, Narendra"'

3. Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors

Author

Cheema, Suraj S, Shanker, Nirmaan, Wang, Li-Chen, Hsu, Cheng-Hsiang, Hsu, Shang-Lin, Liao, Yu-Hung, San Jose, Matthew, Gomez, Jorge, Chakraborty, Wriddhi, Li, Wenshen, Bae, Jong-Ho, Volkman, Steve K, Kwon, Daewoong, Rho, Yoonsoo, Pinelli, Gianni, Rastogi, Ravi, Pipitone, Dominick, Stull, Corey, Cook, Matthew, Tyrrell, Brian, Stoica, Vladimir A, Zhang, Zhan, Freeland, John W, Tassone, Christopher J, Mehta, Apurva, Saheli, Ghazal, Thompson, David, Suh, Dong Ik, Koo, Won-Tae, Nam, Kab-Jin, Jung, Dong Jin, Song, Woo-Bin, Lin, Chung-Hsun, Nam, Seunggeol, Heo, Jinseong, Parihar, Narendra, Grigoropoulos, Costas P, Shafer, Padraic, Fay, Patrick, Ramesh, Ramamoorthy, Mahapatra, Souvik, Ciston, Jim, Datta, Suman, Mohamed, Mohamed, Hu, Chenming, and Salahuddin, Sayeef

Subjects
Engineering, Physical Sciences, Condensed Matter Physics, General Science & Technology
Abstract

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO2 (ref. 2), which remains the material of choice to date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials.

Published
2022

22. BAT Framework Modeling of RMG HKMG SOI FinFETs

Author

Parihar, Narendra, primary, Choudhury, Nilotpal, additional, Samadder, Tarun, additional, Sharma, Uma, additional, Southwick, Richard, additional, Wang, Miaomiao, additional, Stathis, James H., additional, and Mahapatra, Souvik, additional

Published
2021
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34. A Generic Trap Generation Framework for MOSFET Reliability—Part I: Gate Only Stress–BTI, SILC, and TDDB

Author

Mahapatra, Souvik, Ansari, Aseer, Bisht, Arnav Shaurya, Choudhury, Nilotpal, Parihar, Narendra, Chatterjee, Payel, Gholve, Prasad, Tiwari, Ravi, Kumar, Satyam, and Samadder, Tarun

Abstract

The Reaction-Diffusion-Drift model is validated as a trap generation framework during Bias Temperature Instability (BTI), Stress Induced Leakage Current (SILC), and Time Dependent Dielectric Breakdown (TDDB) experiments. The model is implemented in standalone and Technology CAD (TCAD)-based deterministic and standalone stochastic versions. Different implementations show equivalence of the time kinetics of trap generation during stress and trap passivation after stress. The trigger for different type of experiments is introduced via a single reaction parameter. The model is validated against measured data under diverse experimental conditions, either solely, or along with other models to account for additional physical processes. A circuit simulation platform that uses the physical trap generation model is utilized to estimate activity aware aging in logic circuits due to BTI. The error associated with effective AC duty simulation is shown. Implementation and validation for the Hot Carrier Degradation (HCD) is presented in part-II of this article.

Published
2024
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37. Plasma Charging Damage in HK-First and HK-Last RMG NMOS Devices

Author

Hiblot, Gaspard, primary, Parihar, Narendra, additional, Dupuy, Emmanuel, additional, Mannaert, Geert, additional, Baudot, Sylvain, additional, Kaczer, Ben, additional, Franco, Jacopo, additional, Vandooren, Anne, additional, De Heyn, Vincent, additional, and Mercha, Abdelkarim, additional

Published
2021
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38. Error Analysis of Sine-Cosine Computation using CORDIC Algorithm

Author

Nandoskar, Aarushi, Parihar, Narendra, Yadav, Surya Prakash, Gupta, Shrey, and Sahu, Shridhar

Abstract

Background: Coordinate Rotation Digital Computer (CORDIC) can be used for computing trigonometric functions like sine and cosine for which it iterates over a for loop and performs rotation of the input angle. Methods: On the basis of the condition, it decides addition and subtraction operations to compute the sine and cosine values. In general, for each iteration in the CORDIC algorithm, it produces 1 extra bit of accuracy. This paper presents an in-depth survey of the many changes to the CORDIC algorithm proposed over recent years. An efficient method to calculate the sine and cosine of an input angle using the CORDIC algorithm with minimum hardware requirement is presented here. Results: CORDIC algorithm is implemented for 8 bits, 16 bits and 32 bits input and the average percentage error obtained as the results are 1.67%, 0.003785% and 0.003290% respectively. Conclusion: It can be seen that by increasing the number of bits, the accuracy increases. For a complete survey, discussions addressing the CORDIC algorithm are also presented.

Published
2023
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