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We investigated 60-nm In0.52Al0.48As/In0.53Ga0.47As pseudomorphic high-electron mobility transistors (p-HEMTs) fabricated by using a Ne-based atomic-layer-etching (ALET) technology. The ALET process produced a reproducible etch rate of 1.47 Å/cycle for an InP etch stop layer, an excellent InP etch selectivity of 70 against an In0.52Al0.48As barrier layer, and an rms surface-roughness value of 1.37 Å for the exposed In0.52Al0.48As barrier after removing the InP etch stop layer. The application of the ALET technology for the gate recess of 60-nm In0.52Al0.48As/In0.53Ga0.47As p-HEMTs produced improved device parameters, including transconductance (GM), cutoff frequencies (fT), and electron saturation velocity (Vsat) in the channel layer, which is mainly due to the high etch selectivity and low plasma-induced damage to the gate area. The 60-nm In0.52Al0.48As/In0.53Ga0.47As p-HEMTs fabricated by using the ALET technology exhibited GM,Max = 1.17 S/mm, fT = 398 GHz, and Vsat = 2.5 x 107 cm/s. [ABSTRACT FROM AUTHOR]

The characteristics of 0.15-μm InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In0.52Al0.48As barrier and showed a much higher etch selectivity (~70) of the InP spacer against the In0.52Al0.48As barrier. The 0.15-μm InAlAs/InGaAs p-HEMTs that were fabricated using the ALET exhibited improved GM,max (1.38 S/mm), ION/IOFF(1.1S x 104), drain-induced barrier lowering (80 mV/V), threshold voltage uniformity (Vth,avg = -190 mV and σ = 15 mV), and ƒT (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area. [ABSTRACT FROM AUTHOR]