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In this work, a leaky-Ferroelectric Field Effect Transistor (FeFET) neuron is introduced as a physical reservoir in a reservoir computing scheme. Compared to a conventional FeFET reservoir control sample, which did not show leaky behavior, the proposed leaky-FeFET neuron-based physical reservoir exhibited 78.6% and 62.9% improvements in memory capacity for Short Term Memory (STM) and Parity Check (PC) tasks, respectively. The improvements are attributed to the temporal memory effect induced by the leaky-integrating neuronal behavior, which originates from the retention degradation of the FeFET.

In this study, we report on the fabrication and characterization of 3-D sequential complementary field-effect-transistors (CFETs) using the direct wafer bonding (DWB) technology and a low-temperature process for monolithic 3-D (M3D) integration. The device features a high-performance top Ge (110)/ $\langle 110\rangle $ channel on a bottom Si CMOS. To ensure high performance without causing damage to the bottom Si n-FETs, the maximum thermal budget during the fabrication of the top Ge p-FETs was limited to 400 °C. We systematically investigated the mobility enhancement of the thin Ge (110) nanosheet (NS) channel p-FETs as a function of channel orientation. Our results demonstrate that the low effective hole mass along the $\langle 110\rangle $ direction on Ge (110) wafer provides record-high mobility of 400 cm2/ $\text{V}\cdot \text{s}$ (corresponding to 760 cm2/ $\text{V}\cdot \text{s}$ when normalized by footprint) at room temperature, which is the highest reported among the Ge p-FETs with similar channel thicknesses.

Monolithic 3-D (M3D) integration has been spotlighted as an approach to overcome the limitation of classical scaling in integrated circuits (IC). However, the fabrication of the top-tier devices in M3D is challenging because of the limited maximum thermal budget during the integration process. In this work, a nanosecond annealing process using a pulsed green laser is introduced to fabricate the top-tier devices and minimize the thermal influence on the bottom-tier devices. With green laser, the average temperature gradient along the vertical direction within top-tier devices was reduced as much as 26%, compared to excimer laser. The pulsed green laser annealing effectively activated the dopant to form the source/drain of top-tier devices, which showed lower contact resistance ( ${R}_{c}$ ) by around 38% compared to the case of rapid thermal annealing (RTA) process. Furthermore, the nanosecond green laser annealing achieved a lower equivalent oxide thickness (EOT) and 63% reduction of interface trap density ( ${D}_{\text {it}}$ ) of high- ${K}$ gate dielectric in the top-tier MOS devices, leading to smaller subthreshold swing (SS) and enhanced effective mobility up to 13% and 29%, respectively, compared to the use of RTA.