135 results on '"Parrilla, L."'
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2. Comments on “Fast architecture for decimal digit multiplication”
3. Improvements for the applicability of power-watermarking to embedded IP cores protection: e-coreIPP
4. Efficient wavelet-based ECG processing for single-lead FHR extraction
5. P1284: LIQUID BIOPSY BY ULTRA-DEEP SEQUENCING PLUS PET-TC MONITORING IN REAL-LIFE FOLLICULAR LYMPHOMA PATIENTS
6. An application of reconfigurable technologies for non-invasive fetal heart rate extraction
7. Adaptive cooperation between processors in a parallel Boltzmann machine implementation
8. The graviton Compton mass as Dark Energy
9. 23P CDK4/6 inhibition and endocrine therapy (ET) in the HER2-enriched subtype (HER2-E) in hormone receptor-positive/HER2-negative (HR+/HER2-) advanced breast cancer (ABC): A retrospective analysis of real-world data
10. Implementation of High-Performance PID Controllers Using RNS and Field-Programmable Devices
11. Efficient image-based analysis of fruit surfaces using CCD cameras and smartphones
12. Parametrized ECT processing over FPGA for a reconfigurable application
13. Towards Project-Based Learning applied to the Electronic Engineering studies
14. Hardware implementation of a new ECC key distribution protocol for securing Wireless Sensor Networks
15. P117 Axillary residual disease after neoadjuvant treatment according to disease burden in the sentinel lymph node biopsy.
16. Design Time Optimization for Hardware Watermarking Protection of HDL Designs
17. Compact cryptoprocessor for securing wireless communications in FECG portable instrumentation
18. Quemoradiotherapy (CRT) in locally advanced esophageal cancer: Single center experience
19. Noise Suppression in ECG Signals through Efficient One-Step Wavelet Processing Techniques
20. Minimum-clock-cycle Itoh-Tsujii algorithm hardware implementation for cryptography applications over GF(2m) fields
21. Design of a Middleware Interface for ARINC 429 Data Bus
22. Intellectual property protection (IPP) using obfuscation in C, VHDL, and Verilog coding
23. Watermarking strategies for IP protection of micro-processor cores
24. Design and performance of an adaptation middleware interface for a civil avionic bus
25. Real time sensor acquisition platform for experimental UAV research
26. New advances for automated IP soft-core watermarking
27. Intellectual Property Protection of IP Cores at HDL Design Level with Automatic Signature Spreading
28. HDL-level automated watermarking of IP cores
29. Intellectual property protection of IP cores through high-level watermarking
30. Ring oscillators as thermal sensors in FPGAs: Experiments in low voltage.
31. Protection of microprocessor-based cores for FPL devices.
32. New advances for automated IP soft-core watermarking.
33. Enhanced gradient-based motion vector coprocessor.
34. HDL-level automated watermarking of IP cores.
35. Automated Signature Insertion in Combinational Logic Patterns for HDL IP Core Protection.
36. Intellectual property protection of IP cores through high-level watermarking.
37. Digital Signature Embedding Technique for IP Core Protection.
38. IPP Watermarking Technique for IP Core Protection on FPL Devices.
39. RNS-based Watermarking for IP Cores.
40. Watermarking strategies for RNS-based system intellectual property protection.
41. RNS-FPL merged architectures for orthogonal DWT
42. Nondeterministic AND-EXOR minimisation by using rewrite rules and simulated annealing
43. Using simulated annealing in the minimisation of AND-EXOR functions
44. Intellectual property protection (IPP) using obfuscation in C, VHDL, and Verilog coding
45. Multiprotocol CWDM network for refueling vision system.
46. ECG processing on reconfigurable hardware for efficient artifact reduction
47. Novel RNS-based SIMD RISC processor for digital signal processing
48. One-step wavelet-based processing for wandering and noise removing in ECG signals
49. Parametrized ECT processing over FPGA for a reconfigurable application
50. Modified boltzmann machine for an efficient distributed implementation
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