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This paper presents an analysis of load-pull measurement data of a GaN on SiC high electron mobility transistor (HEMT) at 3.6 GHz, oriented to aid the design of Doherty power amplifiers with multiple DC supply voltages. Fundamental load-pull data in class AB configuration are analyzed to realize the optimum load modulation for the design of the “Main” amplifier at DC bias levels of 28 V and 50 V.

This paper explores the use of the Cardiff non-linear behavioral model to characterize the response of multiple-input power amplifiers. In particular, a case study is presented on a 300 W load modulated balanced amplifier operating at 2.1 GHz. The model mathematical formulation is presented, and the comparison between original data and model shows an error below 3%. More importantly, it is shown that the model can accurately interpolate between characterization points allowing a reduction of up to 96% of the points needed to accurately predict the model behavior. This significantly reduces the simulation and measurement time for multiple-input PA's whilst attempting to determine the optimal driving conditions.

This study reappraises the optimum design parameters for the sequential power amplifier (SPA) when taking relative phase difference into account. By including the phase relationship between the main and peaking amplifiers, a modified efficiency formulation is derived that reveals the impacts of the key design parameters on the SPA efficiency at output power back-off. To optimise a wideband high-efficiency SPA design, a look-up table method is used to predict the required coupling ratio for a wideband directional coupler. To validate the design approach, a 1.5–2.4 GHz SPA is designed and measured, showing drain efficiency higher than 40% at 6 dB back-off across the band. When characterised using a 20 MHz long term evolution (LTE) signal and digital predistortion, the SPA shows good linearity with error vector magnitude

In this Letter, low-pass finite impulse response filters are proposed to flexibly reduce the envelope bandwidth (BW) requirements for envelope tracking (ET) supply modulators. A second-order power ET (PET) approach is used as a comparative study, and a `design zone' for shaping function coefficients is identified for the first time. Proposed 20 and 10 MHz low-pass filters (LPFs) are used to reduce the effective envelope BW in response to a 20 MHz long-term evolution signal applied to a 10 W power amplifier (PA). Experimental results verify that in comparison with PET, the proposed LPF method has the benefit of allowing arbitrary BW reduction and is compatible with the use of customised shaping functions. It is also shown that significant memory effects can be introduced when the effective envelope BW is reduced to less than the RF BW. To investigate the linearisability of the ET PA, the linearity before and after digital pre-distortion is also measured.

This Letter presents a novel characterisation system that is able to fully emulate a complete envelope tracking power amplifier (ET-PA) environment, with modulated impedance synthesis and dynamic supply voltage generation while using industry-standard modulated signals and digital pre-distortion. The system is used to characterise a 10 W GaN device and provide impedance control over the signal and distortion bandwidths, in response to a 10 MHz long-term evolution signal. A National Instruments PXI-based measurement system is utilised to apply tracking signals to a bespoke supply modulator and successfully improve the average power added efficiency by ~18 percentage points. Three different shaping functions are implemented, and their efficiency and linearity performance evaluated. In addition, digital pre-distortion (DPD) is used to linearise the PA while operating with the three different tracking trajectories. Experimental results demonstrate that when applying shaping functions, a trade-off needs to be made between efficiency and linearity. Even though a constant gain shaping function provides lower efficiency, it achieves good raw linearity performance without DPD, which is a good option if local linearisation is not available. This novel system is a useful tool in the design of ET-PAs, to more completely investigate the performance of the device.

Breakdown mechanism in 0.25- μm gate length AlGaN/GaN-on-SiC iron doped high electron mobility transistors (HEMTs) with background carbon is investigated through the drain current injection technique. The measurement results reveal that it can be divided into two distinct stages according to the gate voltage levels. The first stage of the measured drain injected breakdown is mainly due to the initiation of the punchthrough process under the gate, and the second stage of breakdown is associated with the potential barrier between the unintentionally doped (UID) GaN and the Fe doped p-type GaN buffer layer which also has a higher carbon density. The electroluminescence (EL) results suggest that the first stage shows uniform punchthrough current flow, but localized leakage current flow associated with a snapback breakdown mechanism replaces the uniform punchthrough current flow and dominates the second stage. A 2D-TCAD simulation has been implemented and shows the current paths under uniform flow conditions.

A new mathematical formulation for the Cardiff nonlinear behavioral model is presented in this work which includes the dc bias voltages (drain and gate) into the model. It has been verified by modeling a GaN on SiC high electron mobility transistor (HEMT) at 3.5 GHz. For the case presented, interpolation of load-pull data has resulted in a more than 90% reduction in the density of the load-pull data required to generate a nonlinear behavioral model over a wide range of dc bias points.

This letter presents the design of a broadband power amplifier (PA) that achieves, over the 0.45–3.4-GHz frequency band, an output power between 41.5 and 44.3 dBm and a power added efficiency (PAE) higher than 54%. A four-section transformer has been adopted as the output-matching network in order to target the impedance region defined by a simplified prediction of the power and efficiency contours. The designed PA can find application in flexible hardware for 5G applications, as well as in broadband radar and countermeasure systems.

The effects of the nonlinear drain-to-source capacitance ( $C_{\mathrm {DS}}$ ), or the varactor effect, on the operation of continuous-mode class-B/J power amplifiers (PAs) are described in terms of the mathematical analysis as well as experimental validation. The nonlinear $C_{\mathrm {DS}}$ generates harmonic current when the class-B/J drain voltage is applied across it, modifying the theoretical load trajectories on the Smith chart. This is shown to significantly deviate from the continuous-mode assertion of constant power and efficiency. A novel measurement approach called voltage–pull is used to investigate the effects of the second harmonic generation by the varactor in a class-B/J PA mode. Theoretical and experimental results showed the nonlinear $C_{\mathrm {DS}}$ degrades the drain efficiency compared to class-B on one half of the class-B/J design space while improving the other half due to the energy upconversion and downconversion, respectively. This paper provides an approach for die nonlinear characteristic optimizations for transistor manufacturers.

Envelope tracking is one of the promising technologies for 5G power amplifiers, providing high power efficiency over a wide output power range by modulating the supply voltage. Although the baseband impedance, the output impedance of the supply modulator, plays a crucial role in the linearity of the PA, it is often not measured or considered during the modulator design. This paper presents a new, simplified approach to characterising this impedance using a PA with a simple multi-tone modulation as a load. It describes the measurement setup and verifies the results by characterising the baseband impedance of a state-of-the-art buck converter and comparing this to its static model. The results demonstrate that multi-tone signals and complex modulations yield comparable results and are both suitable for measuring and modelling the baseband impedance. This shows that using simple multi-tone measurements and basic equipment, the full static impedance characteristic can be obtained.

An advanced active load-pull pulse profiling (ALPPP) system is presented to identify and track, for the first time, the optimum impedances along different sections of an RF pulse. Optimum impedance variations of a 10W GaN device within the RF pulse, and the resulting performance variations are quantified over an output power range of 25 dB showing a significant variation at power back-off. Furthermore, the nature of optimum load variations is probed through the addition of a pulsed IV capability. Pre-bias is utilized to investigate the impact of traps on device behavior over a range of temperature and drive power levels. It is demonstrated that pre-filling the traps provides for an almost constant load optimum across the RF pulse while maintaining device performance. Moreover, the identified optimum pre-bias condition, shows improved device linearity over the duration of the RF pulse, hence, suggesting a new method for compensating impedance mismatches and improving device linearity within an RF pulse.

This paper demonstrates the first realisation of a sequential power amplifier (SPA) with envelope tracking (ET). Composed of a 10 W main PA and a 23 W peaking PA, the 1.6–2.4 GHz SPA achieves more than 49% drain efficiency at 6 dB back-off across the band through modulating the main PA supply voltage. At 2 GHz, the ET SPA offers more than 45% efficiency at 10 dB back off. Moreover, the linearity of the ET SPA is measured with and without digital predistortion over the band. To the best of the authors’ knowledge, this work is the first investigation where ET has been applied to the SPA.

The aim of this paper is to improve the linearity of an envelope tracking (ET) power amplifier (PA) using a simple baseband linearisation approach (BLA), which releases the requirement for the ET-customised digital predistortion (DPD) techniques. The proposed BLA is verified through the comparative study on a Gallium Nitride (GaN) PA with ET and a 28V supply voltage. A two-tone signal and a 20MHz modulated signal are used in the measurement, which demonstrates that in contrast to the 28 V case, the ET PA using BLA can simultaneously achieve higher efficiency and better linearity. To investigate the linearity improvement of using BLA, the constellation diagrams, AM/AM and AM/PM characteristics with and without generalized memory polynomial (GMP)-based DPD are measured and analysed.

Envelope tracking power amplifiers (ET PAs) are one of the promising architectures to provide high efficiency amplification for future wireless communication systems. This is due to their ability to offer high efficiency over a wide output power range, by modulating the supply voltage applied to the PA. Generating this dynamic supply voltage with switching-mode modulators is highly efficient, but filtering the output remains a challenge, resulting in a residual ‘ripple’ on the supply voltage. This paper presents an experimental investigation into the interaction between a PA and a supply modulator in the presence of this ripple. By adding a varying ripple magnitude to the modulated drain voltage of a 2.14 GHz GaN ET PA with a 10 MHz LTE signal, the effects on the linearity of the RFPA can be observed and analysed to allow the system designer an insight into the amount of ripple that is tolerable, while still being able to achieve linearity and efficiency targets. The mixing products of the ripple and RF signal are shown to be a potential issue in ET PAs. This paper shows, for the first time, the full impact of the ripple voltage magnitude on the output spectrum. Further more, the ripple sensitivity of two different ET PA linearisation approaches are explored; firstly applying generic memory polynomial digital pre-distortion (DPD) and secondly optimising the ET tracking signal shaping function to improve linearity. Measurements show that for the case where the ripple and RF are not synchronized, neither approach is able to significantly mitigate the ripple effect on the PA linearity.

Envelope tracking power amplifiers (ET PAs) are one of the main contenders for high-efficiency PAs in future wireless communication systems. The importance of the input matching network (IMN) in GaN ET PAs is an under-explored topic. This paper explores the impact of the impedance presented to the gate of a transistor by the IMN on linearity, gain and efficiency. The impact is investigated by varying resistance and reactance of the source impedance with a fixed load over a wide range of supply voltages. Based on the results of this investigation, two IMNs are designed, one of which is optimised for maximum gain and the other for a good compromise between gain and linearity. Simulations show that the trade-off IMN achieves comparable power added efficiency (PAE) while the AM/PM distortion was reduced by more than 40%. The reduction in Q-factor of the input impedance is another advantage, possibly facilitating broadband matching. To verify these assumptions, a 2.9 GHz 10 W GaN RFPA was manufactured and measured. While measurements and simulations diverged to the degree expected from literature, they demonstrate that an input matching network can be used to optimise PAs for linearity in ET systems. A targeted IMN design can reduce phase and gain distortion effectively with little impact on efficiency, and additionally offers the possibility to further trade-off linearity and PAE.

This paper examines the application of a broadband modulated measurement system, and specifically how such a system can be used in combination with active IF load-pull in order to characterize a device whilst operating in an Auxiliary Envelope Tracking (AET). The AET modifies dynamically the instantaneous DC applied to the device through the optimization of baseband impedance. The experimental measurements are carried out on a GaN HEMTs device to investigate the idea of improving the linearity of the device using the very mechanism that is employed to improve efficiency of the device. The investigations have shown a significant improvement in linearity of the device.

Envelope tracking (ET) is a promising power amplifier (PA) architecture for current and future communications systems, which uses dynamic modulation of the supply voltage to provide high efficiency and potentially very wide bandwidth over a large dynamic range of output power. However, the dynamic nature of the supply voltage can lead to a problematic variation in transistor gain, particularly in GaN HEMTs. This paper describes and analyzes this behavior and the detrimental effect it can have on ET PAs. Contributing factors and origins of gain variation are described in detail along with how, for the first time, meaningful comparisons can be made between different devices. Using these guidelines, gain variation is shown to be a widespread issue effecting most GaN HEMTs presented in literature. To allow an analysis of the intrinsic device behavior, an extended transistor model is developed that takes the effect of gate and source field plates into account. This model is refined using measurement data and used to demonstrate the fact that the parasitic gate–drain capacitance ( $C_{\textrm {GD}}$ ) is the main contributor to the small-signal gain variation—a significant part of the overall gain variation. Based on this knowledge, possible strategies to reduce gain variation at the transistor technology level are proposed, allowing the optimization of GaN HEMTs specifically for ET PAs. One identified strategy involves reducing the length of the gate field plate and is shown to be a viable approach to reduce the gain variation in GaN HEMTs, albeit at an increased RF/dc dispersion.

This paper investigates the concurrent operation of a commercially available, modulated impedance synthesis and measurement system with digital pre-distortion (DPD) for industry standard modulated signals. The system was used to characterize a 10W GaN HEMT device, and provide impedance control over signal and distortion bandwidths, in response to a 10 MHz LTE signal centred at 2 GHz, and was able to rapidly achieve target reflection coefficients with an error less than −40dB (1%). A National Instruments (NI) PXi based characterisation system was used to apply a commercially available memory-based DPD algorithm. The transistor was biased in class-AB and was successfully linearised to better than −47.95 dBc ACPR when delivering at 2.5W average output power into an optimum load. Interestingly, the analysis showed that the DPD corrected ACPR contours aligned closely with the P 1dB contours, confirming the relevance of targeting peak-power for DPD, rather than raw ACPR. Also, and importantly, a level of linearity performance was achieved that meets for example, the 3GPP linearity specifications (45dBc) for commercial deployment, and demonstrates how this modulated load-pull system and DPD can be combined to de-risk an amplifier design at a very early stage in the design process.

This paper demonstrates a novel approach to reduce the density of load-pull measurements that are required to populate a high-density Cardiff behavioural model coefficient look-up table, versus input drive signal, covering a large dynamic range. The presented approach investigates the use of coefficient interpolation to achieve this objective using a recently published re-formulation of the Cardiff behavioural model. This approach provides global interpolation functions for the model coefficients with respect to input drive level (|a 11 |). It is shown that this approach can provide for accurate interpolation of load-pull behaviour over a 2-4 dB power range. This knowledge can be used to reduce the number of measurements necessary, hence the time duration required, to populate the Cardiff behavioural model look-up table, without compromising accuracy when used in CAD simulations. The techniques are demonstrated on a 10W packaged Cree HFET.

This paper presents a new measurement and data analysis approach for both identifying the required Cardiff behavioural model complexity and directly extracting the associated model coefficients, K p,h,m,n . The technique developed utilizes a multi-tone measurements approach. Load-pull measurements are performed using an engineered multi-tone active load-pull excitation, A 21 (t), that is chosen for its ability to identify the required model complexity. Fast Fourier Transforming (FFT) the device response, B 21 (t), allows the respective model mixing order contributions to be directly observed above the noise floor of the measurement system. Formulating the Cardiff behavioural model in the frequency domain, with this selected multi-tone stimulus, also allows for the first time the direct extraction of the model coefficients.

This paper presents a new technique for identifying the mixing structure, model coefficients and therefore model order of the Cardiff behavioral model for phase related nonlinearities. The technique employs a two-tone measurements approach and the Fast Fourier Transform (FFT) to be able to observe the mixing structure above the noise floor of the measurement system. Spectral tone visibility explicitly requires model coefficient inclusion for accurate (NMSE

Intrinsic limits to temperature-dependent substrate loss for GaN-on-Si technology, due to the change in resistivity of the substrate with temperature, are evaluated using an experimentally validated device simulation framework. Effect of room temperature substrate resistivity on temperature-dependent CPW line loss at various operating frequency bands are then presented. CPW lines for GaN-on-high resistivity Si are shown to have a pronounced temperature-dependence for temperatures above 150{\deg}C and have lower substrate losses for frequencies above the X-band. On the other hand, GaN-on-low resistivity Si is shown to be more temperature-insensitive and have lower substrate losses than even HR-Si for lower operating frequencies. The effect of various CPW geometries on substrate loss is also presented to generalize the discussion. These results are expected to act as a benchmark for temperature dependent substrate loss in GaN-on-Si RF technology., Comment: 7 pages (double-column), 10 figures

Non-linear frequency-domain I-V behavioral models have recently been proposed as an alternative to A-B behavioral models. Admittance formulation is suitable for model scaling with device size and fundamental frequency, very convenient for MMICs CAD. But direct extraction from NVNA measurements, easy to perform with A-B models, is difficult, since we need to account for input variations. Hence determining the required model complexity to aid in the extraction/modelling process becomes a key issue. In this paper, a systematic investigation of the Admittance model complexity requirements to obtain sufficiently accurate model predictions suitable for microwave power amplifier design requirements, is performed. Agencia Estatal de Investigación | Ref. TEC2017-88242-C3-2-R Ministerio de Economía y Competitividad | Ref. TEC2014-60283-C3-3-R

This paper evaluates the applicability of pulsed I – V measurements as a tool for accurately extracting nonlinear gallium nitride (GaN)-based heterojunction field-effect transistor (HFET) models. Two wafers with the identical layer structure but different growth conditions have been investigated. A series of I – V measurements was performed under dc and pulsed conditions demonstrating a dramatic difference in the kink effect and current collapse (knee walkout) suggesting different trapping behaviors. However, when radio frequency (RF) I – V waveform measurements, utilizing active harmonic load–pull, were used to study the impact of these traps on the RF performance, both wafers gave good overall RF performance with no significant difference observed. This absence of correlation between pulsed I – V measurement results and RF performance raises a question about the applicability of pulsed I – V measurements alone as a tool for extracting nonlinear device models in the case of GaN HFETs.

Comparison between pulsed and CW large signal RF performance of field-plated $\beta $ -Ga2O3 MOSFETs has been reported. Reduced self-heating when pulse resulted in a power added efficiency of 12%, drain efficiency of 22.4%, output power density of 0.13 W/mm, and maximum gain up to 4.8 dB at 1 GHz for a 2- $\mu \text{m}$ gate length device. Increased power dissipation for higher ${V} _{\textsf {DS}}$ and ${I} _{\textsf {DS}}$ resulted in a degradation in performance, which, thermal simulation showed, could be entirely explained by self-heating. Buffer and surface trapping contributions have been evaluated using gate and drain lag measurements, showing minimal impact on device performance. These results suggest that $\beta $ -Ga2O3 is a good candidate for future RF applications.

We demonstrate that the highly-resistive Si substrate in GaN-on-Si RF HEMTs does not act as an insulator, but instead behaves as a conductive ground plane for static operation and can cause significant back-gate induced current collapse. Substrate ramp characterization of the buffer shows good agreement with device simulations and indicates that the current collapse is caused by charge-redistribution within the GaN layer. Potential solutions which alter charge storage and leakage in the epitaxy to counter this effect are then presented.

In the design of power amplifiers, it is necessary to model the transistor behaviour at high compression levels and accurately predict load-pull power and efficiency contours as well as harmonics. For this purpose, nonlinear behavioural model approaches have been successfully used, like Cardiff model. In this paper, a systematic study is presented on the complexity required for the Cardiff model to achieve a given precision when targeting different load-pull contour design requirements for a GaN HFET. The study has been performed through simulation and measurements and is aimed at providing a systematic approach to aid in the extraction of accurate and efficient Cardiff behavioural models. Ministerio de Economía y Competitividad | Ref. TEC2014-60283-C3-3-R Agencia Estatal de Investigación | Ref. TEC2017-88242-C3-2-R

This paper presents the formulation of a behavioral model for a gallium nitride (GaN) Doherty power amplifier (DPA) using long short-term memory (LSTM) networks. Implemented in TensorFlow, LSTM networks can construct the dynamic behavior with memory effects by learning the useful patterns in the time domain. The behavioral model is built using the measured in-phase and quadrature ($\boldsymbol {I}$/$\boldsymbol {Q}$) data of the DPA, under excitation by a 20-MHz LTE signal. A comparative study indicates that the LSTM model is capable of accurately capturing the AM/AM and AM/PM characteristics of the DPA, as well as achieving competitive accuracy when compared to Volterra-based models.

Envelope tracking power amplifiers (ET PAs) are one of the main contenders for future communication systems. Their operation over a wide range of supply voltages ($V_{\text{D}})$ leads to an extended set of requirements, this paper investigates a number of technologies, including Si LDMOS, GaAs pHEMT and GaN HEMT and how they behave in broadband ET PAs. The increased impact of the feedback capacitance $C_{\text{GD}}$ on broadband PA design in HEMT devices caused by a reduced $V_{\text{D}}$ is described for the first time. Analysis of the $V_{\text{D}}$ dependent characteristics show that GaN HEMTs can exhibit the most promising behaviour for broadband ET PAs due to their favourable output voltage dependent gain variationand their low capacitance to power ratio, so long as field plate designs are used to guarantee a favourable knee walkout.

This paper discusses, for the first time, the continuity\ud of optimum load for power and efficiency in saturated GaN\ud devices. Continuous modes are defined originally on the zerograzing\ud voltage assumption. In this paper we show that a\ud continuous behaviour can also be observed in saturated devices\ud without imposing any limitation on clipping. Simulations using a\ud simplified knee-model for the device and source-load pull experimental\ud characterization are critically analysed and compared to\ud describe the discovered continuum.

This paper investigates and compares the use of nonlinear test-set models for an effective and accurate operation of active load-pull systems. The results demonstrate a simple-to-implement and yet robust technique to align the generator and receiver reference plane with a minimum set of required measurements. With only 14 measurements a high agreement between target and measured load points was achieved with an average error less than 0.1 dB over a 70dB dynamic range. An increase in modeling complexity has therefore yielded no improvement. To compare the results, a behavioral model was employed, and it is shown that a high order of model complexity is required to achieve the same level of accuracy. The presented work provides, for the first time, a practical and effective method for the modeling of test-set nonlinearities, hence allowing a cost-effective implementation of active load-pull systems that operate power amplifiers within a gain compression region.

The CAD design of Power Amplifiers requires an accurate non-linear modelling solution. Generally, this is provided by state function (1-V, Q-V) model formulations. These typically require time consuming measurement procedures for model extraction and verification. Look-up table a-wave based behavioral models, i.e. the Cardiff Model, extracted directly from measurement data provide for a robust alternative, addressing both simulation accuracy and model extraction time. The challenge is identifying, in a time efficient manner, the appropriate load-pull impedance space, that ensures the model coefficients are accurately extracted. This paper outlines an automated approach addressing this requirement, that exploits the novel features of emerging high-speed load-pull measurement systems to identify and then measure directly load-pull power contours. The automated approach reduces significantly the number of required measurements, hence the measurement time, compared with the traditional approach while also ensuring an accurate Cardiff Model is extracted. The approach is demonstrated on a 10W packaged Cree HFET.

RF DC/DC converters typically treat power amplifier and rectifier separately. This paper presents a novel approach to designing converters based on the interaction between amplifier and rectifier. By utilising the second harmonic power generated in the rectifier to realise second harmonic injection to the power amplifier, both can be operated at high efficiency. This waveform engineering based concept is explored mathematically and then simulated. Based on this analysis, a class $\mathrm{B}^{*}$ rectifier based on a 0.25 $\mu \mathrm{m}6\mathrm{x}80\mu \mathrm{m}\mathrm{G}\mathrm{a}\mathrm{N}$ HEMT is measured using a load-pull/source-pull measurement system to emulate the required harmonic impedance environment. The resulting voltage and current waveforms are de-embedded to the intrinsic current generator plane and analysed, confirming the ability of this kind of rectifier to provide beneficial second harmonic injection to a power amplifier. The rectifier‘s efficiency is measured to be more than 90% over an input power range of 20 dB if the generated second harmonic is taken into account.

This paper introduces a novel method that allows the presentation of specific, broadband impedances to a DUT by loadpull. To investigate this method, a derivative of class J power amplifier termed BJ is emulated, which effectively lies between class J and class B along the reactive routes on the Smith chart. The mode helps explore baseband linearization approach and its suitability when using continuous mode architectures. Adopting out-of-band impedance optimization technique allows to present impedances and move progressively from a completely real set of loads to completely imaginary set of loads in a deterministic and systematic way. This further extends a view to look at how well the emulated mode linearizes at a set of BJ contour points along the way. The method uses multiple modulated signal sources, phase synchronized at both radio frequency (RF) and intermediate frequency (IF) to provide a complete multi-harmonic broadband loadpull capability controlled by a single local oscillator and allows complete impedance control at the DUT current generator plane.

This paper discusses the analysis and the experimental results of a load modulated balanced amplifier designed for base-station applications. The hardware, employing commercially available GaN packaged devices, operates in the 1.7–2.5 GHz band, with maximum output power higher than 63 W, and with power added efficiency higher than 43% and 39% at 6 dB and 8 dB output power back-off, respectively. The analysis reveals that the proposed topology has some advantages when compared to other load modulated amplifiers, such as the Doherty, but on the other hand it shows an intrinsic non-linear behaviour. This is confirmed by experimental results, where it is shown that employing a non-linear splitting function between the two branches of the amplifier improves the performances with respect to a linear splitter. Moreover, through the adoption of a proper digital splitting function and predistortion it is possible to linearize the amplifier to a level acceptable for Long Term Evolution (LTE) base-stations while maintaining a competitive average efficiency.

It has been established that the terminal radio frequency (RF) current and voltage (IV) waveforms are the unifying theoretical link between transistor technologies, circuit design, and system performance, and therefore, greatly influence the radio frequency power amplifier’s (RFPAs) performance [1]. Thus, it has become necessary to carry out detailed analysis of the time-varying RF voltage V(t) and current I(t) waveforms present on the device terminals for optimizing the output power and dc to RF power conversion efficiency of RFPAs. Alternatively, it can also be said that it has become a standard practice to identify the mode of operations of RFPAs by analyzing the V(t) and I(t) waveforms measured or simulated at the intrinsic terminals of the transistor. For example, Class A and Class F power amplifiers are represented by their respective current and voltage waveforms, as depicted in Fig. 1. It is apparent that in Class A, both the current and voltage waveforms are sinusoidal about the bias point, whereas in Class F, the current waveform is a half-wave rectified sinusoid, and the voltage waveform is a square wave [2], [3]. To experimentally support these established theoretical postulations with regard to current and voltage waveforms, there is a need for Waveform Engineering systems. In principle, waveform engineering is the ability to modify, in a quantified manner, the time-varying current and voltage waveforms present at the terminals of the transistor devices by changing the fundamental and harmonic impedances seen by the intrinsic transistor‘s access points. Effectively, the waveform engineering systems consist of two aspects, namely a waveform measurement component [1], [4], [5] and impedance tuning elements called the load-pull systems [6]–[8].