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An assessment of radio network coverage, usually in the form of a measurement campaign, is essential for multi-base-station (multi-BS) network deployment and maintenance. It can be conducted by a network operator or its served consumers. However, the number of measurement points and their locations may not be known in advance for an efficient and accurate evaluation. The main goal of this study is to propose a new methodology for understanding the selection of measurement points during coverage and signal quality assessment. It is particularly tailored to multi-BS low-power wide-area network (LPWAN) deployments without explicit knowledge of BS locations. To this aim, we first conduct a large-scale measurement campaign for three popular LPWAN technologies, namely, NB-IoT, Sigfox, and LoRaWAN. Utilizing this baseline data, we develop a procedure for identifying the minimum set of measurement points for the coverage assessment with a given accuracy as well as study which interpolation algorithms produce the lowest approximation error. Our results demonstrate that a random choice of measurement points is on par with their deterministic selection. Out of the candidate interpolation algorithms, Kriging method offers attractive performance in terms of the absolute error for NB-IoT deployments. By contrast, for Sigfox and LoRaWAN infrastructures, less complex techniques, such as Natural-neighbor, Linear interpolation, or Inverse-Distance Weighting, can achieve comparable (and occasionally even better) accuracy levels. acceptedVersion

The research addresses implementation of custom internal mechanisms of computational process management abstractly from application functionality in hardware design. Explicit allocation of “microarchitectural middleware” design level is proposed. The key design components used at this level are custom programmable and synthesizable execution kernels — “micro-language” IP (MLIP) cores. The supporting framework is being developed by the authors. Experimental designing based on MLIP approach has demonstrated significant (up to 63%) code reusability for hardware cores that do not have any common structural submodules but do share custom internal scheduling and synchronization mechanisms that are cross-cutting relative to the hardware cores structure.

Dynamic blockage of radio propagation paths between the user equipment (UE) and the 5G New Radio (NR) Base Station (BS) induces abrupt rate fluctuations that may lead to sub-optimal performance of the Transmission Control Protocol (TCP) protocol. In this work, we characterize the effects of dynamic human blockage on TCP throughput at the 5G NR air interface. To this aim, we develop an analytical model that expresses the TCP throughput as a function of the round-trip time (RTT), environmental, and radio system parameters. Our results indicate that the blockage affects TCP throughput only when the RTT is comparable to the blocked and non-blocked state durations when the frequency of state changes is high. However, such conditions are not typical for dynamic body blockage environments allowing TCP to benefit from the high bandwidth of 5G NR systems fully.

Interleaving is a mechanism universally used in wireless access technologies to alleviate the effect of channel correlation. In spite of its wide adoption, to the best of our knowledge, there are no analytical models proposed so far. In this paper we fill this void proposing three different models of interleaving. Two of these models are based on numerical algorithms while one of them allows for closed-form expression for packet error probability. Although we use block codes with hard decoding to specify the models our modeling principles are applicable to all forward error correction codes as long as there exists a functional relationship (possibly, probabilistic) between the number of incorrectly received bits in a codeword and the codeword error probability. We evaluate accuracy of our models showing that the worst case prediction is limited by 50% across a wide range of input parameters. Finally, we study the effect of interleaving in detail demonstrating how it varies with channel correlation, bit error rate and error correction capability. Numerical results reported in this paper allows to identify the optimal value of the interleaving depth that need to be used for a channel with a given degree of correlation. The reference implementations of the models are available [1] .

Stochastic geometry has recently gained popularity for performance assessment of wireless networks. The application of this approach is conditioned on the availability of the closed-form expressions for probability distributions of the distance between the receiver and interfering nodes. These expressions are available for the simple point processes, e.g., the Poisson point process, and area geometries only. The motivation of this letter is to draw the attention of the wireless research community to a new methodology for estimating interference in spatially random networks. We show that using the integral geometry and working with interference sets rather than interference distances one can approximate the interference for any convex deployment areas and general distribution of interfering nodes.

The general-purpose networks-on-chip (GP-NoC) has recently attracted the attention of the research and industry as a way to support the growing demands of computing systems. The design and the development of the communications and networking functions for such a large-scale versatile systems require knowledge of the traffic exchanged between the computing nodes. The object of the study in this paper is the last-level shared cache interface that is likely to be a traffic bottleneck in future GP-NoC architectures. First, using the direct measurements, we report on the stochastic traffic properties at large-scales, provide first two moments and distribution functions. Complementing measurements with fine-grained cycle-accurate CPU simulations, we then analyze the small-scale traffic behavior. We show that even for the simplest applications such as reading or writing of data, the nature of the traffic is stochastic, depends on the number of active cores, and irrespective of the application type, has an explicit batch structure. We further reveal that the batch sizes and inter-batch intervals can be well approximated by geometric distribution and the approximation becomes better when the number of active cores increases. These properties identify a simple arrival model that can be used in the analytical or simulation-based performance evaluation studies of the shared interface technologies in prospective NoCs.

General purpose networks-on-chip (GP-NoC) are expected to feature tens or even hundreds of computational elements with complex communications infrastructure binding them into a connected network to achieve memory synchronization. The experience accumulated over the years in network design suggests that the knowledge of the traffic nature is mandatory for successful design of a networking technology. In this paper, based on the Intel CPU family, we describe traffic estimation techniques for modern multi-core GP-CPUs, discuss the traffic modeling procedure and highlight the implications of the traffic structure for GP-NoC research. The most important observation is that the traffic at internal interfaces appears to be random for external observer and has clearly identifiable batch structure.

The need of rapid design space exploration, early prototype construction and high level of reuse of technical decisions about microarchitecture in hardware design field actualize development of technologies based on custom user-specified hardware generation. However, existing approaches and tools typically offer configurability at the level of predefined set of parameters. In the article, the concept of framework architecture based on Micro-Language IP (MLIP) cores is presented. This approach facilitates creation of lightweight hardware description languages adapted to specific microarchitectural patterns. Furthermore, prototype implementation of the framework is described, followed by description of two experimental MLIP cores, rtl and pipe. These cores provide domain-specific languages for procedural generation of general-purpose RTL and pipelined hardware structures respectively. The developed means have been utilized for rapid designing of educational CPU core that has proved its operational capability in FPGA. We envision complementation of procedural hardware generation approach with microarchitecture-specific DSLs to be promising for raising the level of abstraction in microarchitecture design. This can reduce design duration of complex hardware units by up to two times, assuming either usage of common microarchitectural patterns or embodying of original ones in the new MLIP cores as an integral part of hardware design process.