23 results on '"Pei-Wen Luo"'
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2. Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling.
3. Variation aware optimal threshold voltage computation for on-chip noise sensors.
4. Benchmarking for research in power delivery networks of three-dimensional integrated circuits.
5. Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.
6. Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs).
7. Yield-award placement optimization for Switched-Capacitor analog integrated circuits.
8. Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.
9. Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs.
10. Yield evaluation of analog placement with arbitrary capacitor ratio.
11. DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool.
12. Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits.
13. Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits.
14. Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits.
15. Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
16. A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.
17. From Nanoarchitectonics to Tissue Architectonics: Nanomaterials for Tissue Engineering
18. Contributors
19. Optogenetic Modulation and Reprogramming of Bacteriorhodopsin-Transfected Human Fibroblasts on Self-Assembled Fullerene C60 Nanosheets
20. Self-Assembled Nanosheets: Optogenetic Modulation and Reprogramming of Bacteriorhodopsin-Transfected Human Fibroblasts on Self-Assembled Fullerene C60 Nanosheets (Adv. Biosys. 2/2019)
21. Characterization of Supply and Substrate Noises in CMOS Digital Circuits
22. Characterization of Supply and Substrate Noises in CMOS Digital Circuits.
23. Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits. .
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