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Quantum key distribution (QKD) based on the fundamental laws of quantum physics can allow the distribution of secure keys between distant users. However, the imperfections in realistic devices may lead to potential security risks, which must be accurately characterized and considered in practical security analysis. High-speed optical modulators, being as one of the core components of practical QKD systems, can be used to prepare the required quantum states. Here, we find that optical modulators based on LiNbO3, including phase modulators and intensity modulators, are vulnerable to photorefractive effect caused by external light injection. By changing the power of external light, eavesdroppers can control the intensities of the prepared states, posing a potential threat to the security of QKD. We have experimentally demonstrated the influence of light injection on LiNbO3-based optical modulators and analyzed the security risks caused by the potential green light injection attack, along with the corresponding countermeasures.

Quantum resetting protocols allow a quantum system to be sent to a state in the past by making it interact with quantum probes when neither the free evolution of the system nor the interaction is controlled. We experimentally verify the simplest non-trivial case of a quantum resetting protocol, known as the $\mathcal{W}_4$ protocol, with five superconducting qubits, testing it with different types of free evolutions and target-probe interactions. After projection, we obtained a reset state fidelity as high as $0.951$, and the process fidelity was found to be $0.792$. We also implemented 100 randomly-chosen interactions and demonstrated an average success probability of $0.323$ for $|1\rangle$ and $0.292$ for $|-\rangle$, experimentally confirmed the nonzero probability of success for unknown interactions; the numerical simulated values are about $0.3$. Our experiment shows that the simplest quantum resetting protocol can be implemented with current technologies, making such protocols a valuable tool in the eternal fight against unwanted evolution in quantum systems., Comment: 9 pages, 6 figures, 1 table + Supplementary Materials

We report the preparation and verification of a genuine 12-qubit entanglement in a superconducting processor. The processor that we designed and fabricated has qubits lying on a 1D chain with relaxation times ranging from 29.6 to 54.6 $\mu$s. The fidelity of the 12-qubit entanglement was measured to be above $0.5544\pm0.0025$, exceeding the genuine multipartite entanglement threshold by 21 statistical standard deviations. Our entangling circuit to generate linear cluster states is depth-invariant in the number of qubits and uses single- and double-qubit gates instead of collective interactions. Our results are a substantial step towards large-scale random circuit sampling and scalable measurement-based quantum computing.

Digital-to-analog converter (DAC) and analog-to-digital converter (ADC) as an important part of the superconducting quantum computer are used to control and readout the qubit states. The complexity of instrument manipulation increases rapidly as the number of qubits grows. Low-speed data transmission, imperfections of realistic instruments and coherent control of qubits are gradually highlighted which have become the bottlenecks in scaling up the number of qubits. To deal with the challenges, we present a solution in this study. Based on client-server (C/S) model, we develop two servers called Readout Server and Control Server for managing self-innovation digitizer, arbitrary waveform generator (AWG) and ultra-precision DC source which enable to implement physical experiments rapidly. Both Control Server and Readout Server consist three parts: resource manager, waveform engine and communication interface. The resource manager maps the resources of separate instruments to a unified virtual instrument and automatically aligns the timing of waveform channels. The waveform engine generates and processes the waveform for AWGs or captures and analyzes the data from digitizers. The communication interface is responsible for sending and receiving data in an efficient manner. We design a simple data link protocol for digitizers and a multi-threaded communication mechanism for AWGs. By using different network optimization strategies, both data transmission speed of digitizers and AWGs reach hundreds of Mbps through a single Gigabit-NIC., Comment: 4 pages, 7 figures, 1 table

In this paper, we report an encoding and decoding method for irregular-quasic-cyclic low-density parity-check (IR-QC-LDPC) codes with multi rates. The algorithm is applicable to parity-check matrices which have dual-diagonal parity structure. The decoding adopts normalized min-sum algorithm(NMSA). The whole verification of encoding and decoding algorithm are simulated with MATLAB, if initial bit error ratio is 6% , the code rate of 2/3 is selected, and if the initial bit error ratio is 1.04%, the code rate of 5/6 is selected. We migrate the algorithm from MATLAB to Field Program Gate Array(FPGA) and implement this algorithm based on FPGA. Based on FPGA the throughput of encoding is 183.36Mbps while the average decoding throughput is 27.85Mbps with the initial bit error ratio is 6%., Comment: Rewrite this article

The Superconducting Quantum Computing (SQC) is one of the most promising quantum computing techniques. The SQC requires precise control and acquisition to operate the superconducting qubits. The ultra-precision DC source is used to provide a DC bias for the qubit to work at its operation point. With the development of the multi-qubit processor, to use the commercial precise DC source device is impossible for its large volume occupation. We present our ultra-precision DC source which is designed for SQC experiments in this paper. The DC source contains 12 channels in 1U 19~inch crate. The performances of our DC source strongly beat the commercial devices. The output rang is -7~V to +7~V with 20~mA maximum output current. The Vpp of the output noise is 3~uV, and the standard deviation is 0.497~uV. The temperature coefficient is less than 1~ppm/$^{\circ}$C in 14~V range. The primary results show that the total drift of the output within 48h at an A/C room temperature environment is 40~uV which equal to 2.9~ppm/48h. We are still trying to optimize the channel density and long-term drift / stability., Comment: 3 pages, 4 figures, conference Realtime 2018

Since the 1990s, there has been a dramatic interest in quantum communication. Free-space quantum communication is being developed to ultra-long distance quantum experiment, which requires higher electronics performance, such as time measurement precision, data-transfer rate, and system integration density. As part of the ground station of quantum experiment satellite that will be launched in 2016, we specifically designed a compact PCI-based multi-channel electronics system with high time-resolution, high data-transfer-rate. The electronics performance of this system was tested. The time bin size is 23.9ps and the time precision root-mean-square (RMS) is less than 24ps for 16 channels. The dead time is 30ns. The data transfer rate to local computer is up to 35 MBps, and the count rate is up to 30M/s. The system has been proven to perform well and operate stably through a test of free space quantum key distribution (QKD) experiment.

A high precision and high resolution time-to-digital converter (TDC) implemented in a 40 nm fabrication process Virtex-6 FPGA is presented in this paper. The multi-chain measurements averaging architecture is used to overcome the resolution limitation determined by intrinsic cell delay of the plain single tapped-delay chain. The resolution and precision are both improved with this architecture. In such a TDC, the input signal is connected to multiple tapped-delay chains simultaneously (the chain number is M), and there is a fixed delay cell between every two adjacent chains. Each tapped-delay chain is just a plain TDC and should generate a TDC time for a hit input signal, so totally M TDC time values should be got for a hit signal. After averaging, the final TDC time is obtained. A TDC with 3 ps resolution (i.e. bin size) and 6.5 ps precision (i.e. RMS) has been implemented using 8 parallel tapped-delay chains. Meanwhile the plain TDC with single tapped-delay chain yields 24 ps resolution and 18 ps precision., Comment: IEEE 2014 real time conference record

Up to the present, the wave union method can achieve the best timing performance in FPGA based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code (NTH2B) encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands the encoder to convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder (IFTE) to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constrains were required; therefore, this IFTE structure could also be further applied in other delay chain based FPGA TDCs., Comment: Submitted to "Chinese Physics C"