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This paper investigates CMOS operational transconductance amplifier (OTA) design methodologies suitable for Internet of Things nodes. The use of MOS transistors in the subthreshold of the body terminal for signal input or bias, as well as newer inverter- and digital-based techniques, is considered. Solutions from the authors' work are utilized as main case examples. State-of-the-art ultra-low-power OTAs are then thoroughly compared using a data-driven approach. According to the findings, digital- and inverter-based solutions have the lowest area occupation and superior small-signal performance but are inherently susceptible to process, supply, and temperature (PVT) variations. The only "analog" approach suitable for a sub-0.6 V supply is body driving in conjunction with subthreshold bias. It offers competitive large-signal performance and, more importantly, is less sensitive to PVT variations at the expense of silicon area. [ABSTRACT FROM AUTHOR]

Solutions for the design of low-voltage sample-and-hold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4-[V.sub.PP] differential input signal, the simulated spurious-free dynamic range, signal-to-noise ratio, and total harmonic distortion are 57, 67, and -56 dB (9 equivalent bits), respectively, with low sensitivity to supply, temperature, process, and mismatch variations. The proposed solution employs a three-stage low-voltage amplifier without a tail current source in the differential pair and a switch topology, which combines clock voltage doubling and dummy switches. Index Terms--Bootstrapped switch, nested Miller compensation, sample-and-hold (S/H), very low voltage circuits.

Several design options are nowadays available for the frequency compensation of CMOS two-stage transconductance q operational amplifiers, from the traditional Miller approach employing a nulling resistor or a voltage buffer, to a current buffer or the more modern current amplifier. However, designers have no results on the frequency performance achievable that allow to consciously choose the best approach to meet the prescribed specifications efficiently. In this paper, a comparison among the possible Miller approaches is carried out by exploiting an analytical figure of merit that expresses a tradeoff between gain--bandwidth product, load capacitance, and total transconductance for a given value of phase margin. Interesting and useful results, even unexpected, are found. The accuracy of the comparison is also validated through simulations. Index Terms--Analog integrated circuits, frequency compensation, feedback amplifier, CMOS, multistage amplifier.

The paper presents the derivation of Miller formulas for weakly nonlinear feedback networks. The expressions found are simple and compact and constitute a generalization of the well-known linear case. As an application example, the formulas are applied to a common-emitter amplifier to straightforwardly derive the closed-form expressions of second- and third-harmonic distortion factors. The results found, validated by Spectre simulations with a VBIC bipolar model, allow to understand in depth the contribution of each nonlinear element. Index Terms--Amplifiers, analog circuits, harmonic distortion, Miller theorem, nonlinear network analysis.

Theoretical study and design strategy for Wien oscillator circuits are presented. The analysis takes into account non-linearities and allows to define an optimum design procedure minimizing distortion. The accuracy and viability of both the proposed analysis and design approach are confirmed experimentally. Index Terms--Analog circuits, circuit optimization, harmonic distortion, nonlinear network analysis, oscillators.

Two internally compensated CMOS current-feedback operational amplifiers are discussed in this paper. The circuits are entirely made up of class AB stages, thereby increasing slew rate and drive capability, avoiding many of the drawbacks incurred by previous CMOS and even bipolar implementations. Experimental results on one prototype fabricated in a 0.35-[micro]m process using a 20-pF load and supplied with 3.3 V are also given, showing, as main performance parameters, a SR of 35 V/[micro]s and a constant closed-loop bandwidth (in inverting configuration with a 10- [ohm] feedback resistor) of about 2 MHz. Index Terms--Amplifiers, CMOS, current-feedback operational amplifiers (CFOAs).

A mixed-signal universal architecture able to emulate the behavior of an n-port analog circuit is presented. It exploits second-generation current conveyors as analog input/output blocks and a field programmable gale array circuit as digital processing element. A prototype is also discussed for the specific case of a two-port network synthesis and experimental results in agreement with expected ones arc provided. Index Terms--Current conveyor, floating impedance synthesis, network synthesis, vibration damping.

A supplementary linearization technique for CMOS differential pairs with resistive source degeneration is proposed. The approach exploits an auxiliary (degenerated) differential pair to drive the bulk terminals of the main pair. Transistor-level simulations on a design using a 0.25-[micro]m process and powered with 2.5 V and 1 mA, show that total harmonic distortion (THD) in the voltage-to-current conversion is decreased by 10 dB (for an input differential signal with a peak amplitude of 0.5 V and for frequencies up to 100 MHz) compared to the traditional source-degenerated transconductor. This THD improvement is achieved with a negligible increase in power consumption. Index Terms--Analog CMOS circuits, linearization technique, transconductors.

Two CMOS current output stages are presented. Compared to the traditional solution, which exhibits unbalanced operation, the proposed ones exploit an auxiliary high-gain feedback loop which provides differential drive, thereby highly improving the common-mode rejection ratio (CMRR). Prototypes are designed and fabricated in a 0.35-[micro]m technology and experimental results confirm that a CMRR increase greater than 20 dB can be achieved and, for one of the two solutions, without increasing the voltage requirements. Index Terms--Analog electronics, CMOS, current mode, output stage.

The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RNMCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-[micro] m CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included. Index Terms--Analog integrated circuits, CMOS, feedback amplifier, frequency compensation, multistage amplifier.

Design procedures for three-stage CMOS operational transconductance amplifiers employing nested-Miller frequency compensation are presented in this paper. After describing the basic methodology on a Class-A topology, some modifications, to increase swing, slew-rate and current drive capability, are subsequently discussed for a Class-AB solution. The approaches developed are simple as they do not introduce unnecessary circuit constraints and yield accurate results. They are hence suited for a pencil-and-paper design, but can be easily integrated into an analog knowledge-based computer-aided design tool. Experimental prototypes, designed in a 0.35-[micro]m technology by following the proposed procedures, were fabricated and tested. Measurement results were found in close agreement with the target specifications. Index Terms--CMOS, multistage amplifiers, nested-Miller compensation, operational transconductance amplifiers (OTAs).

This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-[micro]m CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances. Index Terms--Frequency compensation, operational transconductance amplifier (OTA), reversed nested Miller (RNM).