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Chemical mechanical planarization (CMP) models which are able to make predictions on the chip and feature scale are highly desirable in semiconductor manufacturing. Most of the models proposed in the past years have largely focused on the pattern density and neglected effects of pattern size in planarization. We here propose a new CMP feature scale model that incorporates size effects by considering the roughness of the polishing pad. It is validated by experimental data from CMP test structures containing variations of both pattern-density and -size. The results are applied to ILD- and STI-CMP as particularly important processes in industry. The derived model describes the feature step height and shape evolution with high accuracy throughout the planarization process.

Chemical mechanical planarization (CMP) models which are able to make predictions for a full chip are highly desirable in semiconductor manufacturing. Previous models proposed to this end have largely focused on effects of pattern density. We here extend one of the proposals to include also effects of pattern-size based on a consideration of the roughness of the polishing pad. Experimental data from CMP test structures containing variations of both pattern-density and pattern-size are used to validate the model. The results are applied to both interlayer dielectric-CMP and shallow trench isolation-CMP as particularly important processes in industry.

Future scaling of complementary metal oxide semiconductor (CMOS) technology requires high-k (HK) dielectrics with metal gate (MG) electrodes to realize higher gate capacitances and low gate leakage currents [1]. During the last decade the semiconductor industry has spent tremendous effort to find the right material. Hafnium-based dielectrics and particularly HfO2 are considered to be the most promising candidates to replace SiON in high volume manufacturing due to their relatively high dielectric constants, large band gap and conduction band offset to Si and their thermodynamic stability with Si [2-4]. However, compared to SiO2, HfO2 dielectrics suffer from threshold voltage instabilities, mobility degradation, charge trapping as well as reliability degradation [5,6]. Recently HfZrO4 has been shown to be a superior gate dielectric to HfO2 [7-11]. Addition of ZrO2 to HfO2 forming HfZrO4 helps to partially stabilize tetragonal phase being associated with higher kand lower CET values [7]. Besides smaller and more uniform grains, more uniform film quality, tighter leakage distribution, less charge trapping, lower CV hysteresis, lower Dit, higher transconductance and drive currents, reduced SILC and longer product reliability lifetimes have been reported among other things for HfZrO4 compared with HfO2 [7-11]. Simultaneously disadvantages like smaller band gap (~0,4eV) and lower conduction band offsets resulting in increased leakage have been presented as well [7]. Up to now atomic layer deposition (ALD) [7-10] as well as physical vapor deposition (PVD) [11] have been explored to form the HfZrO4 layers. As metal-organic chemical vapor deposition (MOCVD) stands out due to excellent manufacturability and high throughputs, we investigate HfZrO4 dielectrics deposited with MOCVD as well as ALD as high-k gate dielectric for 32nm high performance logic SOI CMOS devices in this work. The physical properties of the HfZrO4 films have been analyzed in detail by atom probe tomography [12,13], Xray photoelectron spectroscopy, Rutherford backscattering spectrometry, time-of-flight secondary ion mass spectrometry, transmission electron microscopy, reflectometry, atomic force microscopy, variable angle spectroscopic ellipsometry as well as high temperature grazing incidence X-ray diffraction. In addition electrical parameters such as gate leakage current, capacitance equivalent thickness, threshold voltage, interface trap density (charge pumping) and performance as well as reliability data have been taken into account to directly compare both deposition methods. All parameters indicate a comparable behavior for MOCVD and ALD. Therefore MOCVD is demonstrated to be a promising alternative to ALD in high volume manufacturing in this work.

Eine neue Anlagengeneration fur Abscheide- und Atzprozesse bei der Chipherstellung in der Mikroelektronik hat sich etabliert. Die Systeme erlauben die Integration mehrerer Prozesschritte wie Reinigung, Abscheidung, Atzung und Temperung in einem Vakuumsystem. Der Einsatz wird wesentlich durch die technologische Notwendigkeit der Beherrschung von Grenzflachen im Nanometerbereich sowie der Reduzierung von Partikeln vorangetrieben. Sie bieten aber auch Vorteile bei der Steuerung eines immer komplexeren Fertigungsprozesses mit einer zunehmenden Anzahl von Prozesschritten und einer groseren Produktvielfalt. Hohe Anforderungen werden an die Zuverlassigkeit der Systeme gestellt. A new generation in wafer processing equipment for deposition and etching in the microelectronic chipproduction is established. The systems are capable of multiple, independent processing steps within one vacuum environment for cleaning, deposition, etching and annealing. The implementation is mainly driven by the technological need to control interfaces in the nm range and the reduction of particles. There are also advantages for the control of a production process with increasing complexity and number of process steps with a wider variety of products. High requirements are made on the system reliability.

The mechanisms of technologically important atomic layer deposition (ALD) processes, trimethylaluminium (TMA)/ozone and tetrakis(ethylmethylamino)hafnium (TEMAH)/ozone, for the growth of Al(2)O(3) and HfO(2) thin films are studied in situ by a quadrupole mass spectrometer coupled with a 300 mm ALD reactor. In addition to released CH(4) and CO(2), water was detected as one of the reaction byproduct in the TMA/O(3) process. In the TEMAH/O(3) process, the surface after the ozone pulse consisted of chemisorpted active oxygen and -OH groups, leading to the release of H(2)O, CO(2), and HNEtMe during the metal precursor pulse.

We investigated the effect of post annealing on the electrical and physical properties of atomic-layer-deposited thin HfO2, HfSixOy and HfOyNz gate oxide films on Si. It was found that the main leakage conduction of all Hf-based oxide films was of the Poole–Frenkel (P–F) type in low electric fields and Fowler–Nordheim (F–N) conduction in higher fields. Also, it was observed that the transition from P–F to F–N of the annealed HfOyNz sample occurred earlier than that of the as-grown one. By using spectroscopic ellipsometry, it was found that the annealing process decreased the band gap of HfO2, HfSixOy and HfOyNz films. From depth profile measurements on the HfOyNz film, we conclude that N moves toward the surface and interface during annealing.

The effect of the deposition temperature and layer thickness on the physical and electrical properties of ZrO2-based high-k metal–insulator–metal (MIM) capacitors was studied. The increasing thickness of ZrO2 layer leads to decreasing the leakage current and capacitance of the device. The microstructure investigation shows that after the deposition of the complete MIM stack layer, all samples reveal similar degree of crystallinity, independent of the dielectric deposition temperature, hence it cannot explain completely the different electrical performance of the device. We found that the impurities concentration in the stack decreases as the deposition temperature increases. As a result, we obtain low leakage current (

Micro- and nanoelectronics will see a further extension of Moore's Law with the prediction of a cost reduction of 25% to 30% per year. The introduction of 300 mm technology is one step towards cost reduction. A description of the time lines of the maturization of 300 mm technology reveals the necessity for equipment improvement, especially for the implementation of Advanced Process Control (APC). Examples for APC are given in the fields of fault detection by in situ analysis of plasma parameters and their electrical verification, of an advanced endpoint detection system capable of reliable endpoint detection for a large variety of cleaning reactions and for the reduction of clean durations for chamber wall cleaning in plasma deposition systems, and in the field of the integration of a particle sensor in high temperature furnaces. Another promising technology described in the article is the re-use of 300 mm equipment, especially of cluster tools, targeting at a long term use of equipment by using the highest degree of standardisation and modular processing module integration. Thus, additional nodes of the ITRS, the roadmap for semiconductor technology, can be manufactured without the full investment into new equipment.

For the first time, HfZrO4 dielectrics deposited with metal-organic chemical vapor deposition (MOCVD) as well as atomic layer deposition (ALD) have been investigated as high-k gate dielectric for 32-nm high-performance logic SOI complementary metal-oxide-semiconductor devices in this letter. The composition of the HfZrO4 films has been analyzed in detail by atom probe tomography, Rutherford backscattering spectrometry, and X-ray photoelectron spectroscopy. Optical inline measurements and electrical parameters such as gate leakage current, capacitance equivalent thickness, threshold voltage, and performance as well as reliability data have been taken into account to directly compare both deposition methods. All parameters indicate a comparable behavior for MOCVD and ALD. Therefore, MOCVD has been demonstrated to be a promising alternative to ALD in high-volume manufacturing.

An advanced CMOS scheme for the integration of a graded epitaxial Silicon Germanium (SiGe) layer is presented. SiGe is deposited into the source drain regions right after gate formation to create compressive strain in the transistor channel of the pMOSFETs and thus improve charge carrier mobility. The SiGe layer is exposed to subsequent process steps such as cleaning, implantation and annealing which cause erosion and dopant loss. This effect becomes more severe with increasing Ge content, which is wanted to increase stress in the channel. The negative effect of SiGe erosion on DC transistor performance is shown in this paper and how it can be reduced by optimized SiGe deposition utilizing a two layer stack with different Ge content. First a film with higher Ge concentration is deposited followed by a lower percent Ge film which is aimed to protect the SiGe film underneath. Electrical data for PMOS devices with 55 nm embedded SiGe with 20–30% Ge are presented and compared to the corresponding graded SiGe stack (25–30%, 50 nm with 5 nm thick 15% cap). Comparing Embedded Silicon Germanium (eSiGe) devices with 30 at% Ge, we see a 5% I DSAT improvement for the graded layer over the monolithic one.

Chemical-mechanical planarization (CMP) is one of the most demanding process steps in interconnect integration. Therefore we systematically investigate the planarization of adjacent line-space structures, which emulate IC layouts, as a function of the conditioning process. The interrelation between conditioning, pad roughness and planarization is evaluated by a novel pad roughness characterization methodology. Using this approach, tribological parameters can be correlated to important CMP properties like global step reduction and blanket removal rate, enabling planarization improvements for patterned dielectrics and metals.

A physical vapor deposition tool for 300 mm wafers was coupled with an angle resolved photoelectron spectroscopy tool (ARXPS) and used to study the growth of TaN single layer and TaN/Ta double layer diffusion barriers. The nitrogen content of TaN was adjusted by controlling the nitrogen flow and by varying the deposition power. We describe a process recipe that allows us to decrease the TaN thickness while still maintaining the Ta layer in the low resistivity α-phase. The process recipe was developed on blanket wafers and evaluated in a test structure for high performance CMOS products.

In this paper, we consider the chemical-mechanical planarization (CMP) of adjacent line-space structures with different pattern density. Such structures are used on test-chips for process characterization and provide similar features like typical DRAM layouts. The predictions of previous chip-scale models based on a local balance of forces for this case are scrutinized and it is found that the distribution of the applied pressure between the different density regions is not treated sufficiently accurate in these models. We propose a simple way to include the global force balance and show that the resulting model is able to capture behavior which is more in line with general expectations for the time-evolution of typical CMP processes. The model is calibrated with data obtained for a set of test-structures with varying density and found to give a better match compared to the models described above. Especially, the prediction of the total indicated range, which is a measure for the global planarity after CMP is improved. Additionally, a parametric study shows that qualitatively different removal rate diagrams that confirm engineering experience can be obtained with the new model.

In this work, a possible way to enhance the epitaxial growth of metastable, tensile strained SixC1 − x layers by the addition of germanium is demonstrated. During ultra-high vacuum chemical vapor deposition growth, the co-mixing of germane to the SixC1 − x precursors was found to enhance the growth rate by a factor of ~ 3 compared to the growth of pure SixC1 − x. Furthermore, an increase of the amount of substitutional incorporated carbon has been observed. Selective SixGeyC1 − x − y deposition processes utilizing a cyclic deposition were developed to integrate epitaxial tensile strained layers into source and drain areas of n-channel transistors.

Silicon diffusion from the substrate through Al1-xSixOy thin films was investigated by ToF-SIMS depth profiling. Two types of substrate stacks were analyzed: Si wafer with either native oxide or with additional silicon nitride layer. The amount of diffused silicon depends strongly on the type of the substrate. The activation energy for pure alumina was found to be 2.27 ± 0.02 eV and 3.73 ± 0.02 eV for SiO2/Si and Si3N4/SiO2/Si samples, respectively. Furthermore it was proved that the activation energy increases with higher concentration of Si for SiO2/Si samples whereas it decreases for Si3N4/SiO2/Si. Detailed analysis of SIMS depth profiles provide satisfactory explanation of this phenomenon: SiO2 has much stronger tendency to react with Al1-xSixOy material forming an interface layer that restrain further diffusion of Si from the substrate (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Silicon germanium (SiGe) is considered to substitute silicon (Si) as channel material of p-type MOSFET in future CMOS generations due to its higher hole mobility. In this work we investigate SiGe channels with a germanium concentration of 23 at% and 30 at%, even though the mobility is expected to be higher with even more germanium in the alloy. Low pressure chemical vapor deposition was used for SiGe deposition. A state of the art CMOS process including high-k dielectric and metal gate electrode was applied for fabrication of sub 50 nm gate length devices. As expected from the SiGe channel conduction and valence band offset the threshold voltage of the devices is influenced. The gate stack was directly deposited onto the SiGe layer consisting of a chemically grown base oxide, hafnium-based dielectric and titanium nitride gate electrode. C-V and I-V measurements show comparable CET and leakage values for the high-k metal gate stack on Si and SiGe channels. The trap density at the channel dielectric interface was determined using the charge pumping technique. The device characteristics of n- and p-MOSFETs with SiGe channels are compared to conventional Si channel devices. Short channel mobility was extracted with the gM,LIN-Method.

In this work, the epitaxial growth of Si 1− x C x alloys using an Ultra High Vacuum Chemical Vapor Deposition (UHV-CVD) system was studied. Si 1− x C x layers were grown in a temperature range of 550–650 °C and characterized using rocking curve X-ray diffraction (XRD), atomic force microscopy (AFM) as well as Fourier transform infrared spectroscopy (FT-IR). It was found that with increasing carbon precursor flow (Methylsilane) the amount of substitutional carbon rises up to a critical value. After a maximum in substitutional carbon content is reached, a further increase of carbon fraction leads to a reduction of the strain. By FT-IR, the non-substitutional carbon was determined to form 3C-SiC precipitates already during growth. A strong correlation between the increase of Methylsilane flow and the formation of coherent precipitates even at low carbon fractions was observed. A low deposition temperature was found to promote the precipitation of 3C-SiC.

The direct depth measurement of structures with aspect ratios between 1 and 4 in the arrays of memory cells represents a major challenge for inline metrology. For 75 nm and larger technology nodes these measurements are carried out using inline AFM using 50±5 nm diameter cylindrical AFM probes. However, for 58 nm and smaller technology nodes these AFM probes are not capable anymore, because the tip diameter is comparable to the diameter of the trench structures themselves. Here we report about the development of 30 nm diameter cylindrical AFM probes suitable for direct depth measurements of 58 nm ground rule (GR) structures. The focus of the development was on tip lifetime, gage capability and throughput in a high volume environment. For the tests two different tip materials—silicon (Si) and electron beam deposited (EBD) carbon were investigated. Both tip types proved to be fully gage capable, and showed no throughput losses in comparison to larger node measurements. The tip lifetime under production cond...

Due to the new challenges accompanying every new shrink node in semiconductor industry new materials have to be implemented or device design has to be adapted—both to realize the intended device that still obeys physical laws. Visualization of these problems is a task of metrologists facing themselves physical borders. Monitoring stress becomes a major challenge arising from new processes applied as well as from worse surface to bulk volume‐ratio or intended implied stress in new concepts of devices. High k‐materials might induce macroscopic stress, which can be monitored on the wafer scale in wafer bow experiments. This unintended stress is even higher in patterned areas but not known in a micrometer scale. The knowledge of microscopic stress—or even nanoscopic stress—is even more important on intended stress implemented in devices and thus target of interest. This paper offers two ways of monitoring sub‐micrometer stress. One is the well established scanning Micro‐Raman technique. The second is a relatively new method called Tip‐Enhanced‐Raman‐Spectroscopy (TERS). Both methods have their advantages but also challenges. The results of the easy to use scanning Micro‐Raman technique need to be interpreted and information needs to be unfolded. Whereas the challenge of Tip‐Enhanced‐Raman‐Spectroscopy lies in the experimental skills: handling a scanning‐probe‐microscope‐tip in a Micro‐Raman beam with the perspective of having a resolution restricted only by the SPM‐diameter or even smaller.

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